2020-05-11 21:52:44 -04:00
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: ACIA$
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2020-06-28 17:30:01 -04:00
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H@ DUP DUP [ ACIA( LITN ] ! [ ACIAR> LITN ] !
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1+ [ ACIAW> LITN ] ! ( write index starts one pos later )
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2020-05-11 21:52:44 -04:00
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0x20 ( buffer size ) ALLOT
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2020-06-28 17:30:01 -04:00
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H@ [ ACIA) LITN ] !
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2020-05-11 21:52:44 -04:00
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( setup ACIA
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CR7 (1) - Receive Interrupt enabled
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CR6:5 (00) - RTS low, transmit interrupt disabled.
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CR4:2 (101) - 8 bits + 1 stop bit
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CR1:0 (10) - Counter divide: 64 )
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0b10010110 [ ACIA_CTL LITN ] PC!
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(im1) ;
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