2020-05-11 21:52:44 -04:00
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: (key)
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( inc then fetch )
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2020-08-14 22:51:27 -04:00
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[ ACIAR> LITN ] C@ 1+ [ ACIA_BUFSZ 1- LITN ] AND
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2020-05-11 21:52:44 -04:00
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( As long as R> == W>-1, it means that buffer is empty )
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2020-08-14 22:51:27 -04:00
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BEGIN DUP [ ACIAW> LITN ] C@ = NOT UNTIL
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DUP [ ACIA( LITN ] @ + C@ ( ridx c )
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SWAP [ ACIAR> LITN ] C! ( c )
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2020-05-11 21:52:44 -04:00
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;
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: (emit)
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( As long at CTL bit 1 is low, we are transmitting. wait )
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BEGIN [ ACIA_CTL LITN ] PC@ 0x02 AND UNTIL
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( The way is clear, go! )
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[ ACIA_IO LITN ] PC!
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;
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