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@@ -18,8 +18,7 @@ |
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#define RAMSTART 0x8000 |
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#define ACIA_CTL_PORT 0x80 |
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#define ACIA_DATA_PORT 0x81 |
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#define SDC_CSHIGH 0x06 |
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#define SDC_CSLOW 0x05 |
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#define SDC_CTL 0x05 |
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#define SDC_SPI 0x04 |
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#define MAX_ROMSIZE 0x2000 |
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@@ -56,14 +55,16 @@ static void iowr_sdc_spi(uint8_t val) |
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sdc_spi_wr(&sdc, val); |
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} |
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static void iowr_sdc_cshigh(uint8_t val) |
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// in emulation, exchanges are always instantaneous, so we |
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// always report as ready. |
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static uint8_t iord_sdc_ctl() |
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{ |
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sdc_cshigh(&sdc); |
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return 0; |
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} |
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static void iowr_sdc_cslow(uint8_t val) |
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static void iowr_sdc_ctl(uint8_t val) |
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{ |
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sdc_cslow(&sdc); |
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sdc_ctl_wr(&sdc, val); |
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} |
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int main(int argc, char *argv[]) |
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@@ -117,8 +118,8 @@ int main(int argc, char *argv[]) |
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m->iowr[ACIA_DATA_PORT] = iowr_acia_data; |
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m->iord[SDC_SPI] = iord_sdc_spi; |
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m->iowr[SDC_SPI] = iowr_sdc_spi; |
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m->iowr[SDC_CSHIGH] = iowr_sdc_cshigh; |
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m->iowr[SDC_CSLOW] = iowr_sdc_cslow; |
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m->iord[SDC_CTL] = iord_sdc_ctl; |
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m->iowr[SDC_CTL] = iowr_sdc_ctl; |
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char tosend = 0; |
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while (emul_step()) { |
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