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@@ -27,12 +27,39 @@ the ACIA. |
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## Building the PS/2 interface |
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TODO. I have yet to draw presentable schematics. By reading `ps2ctl.asm`, you |
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might be able to guess how things are wired up. |
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Let's start with the PS/2 connector, which has two pins: |
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It's rather straigtforward: the attiny reads serial data from PS/2 and then |
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sends it to the 595. The 595 is wired straight to D7:0 with its `OE` wired to |
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address selection + `IORQ` + `RO` |
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![PS/2 connector](schema-ps2.png) |
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Both are connected to the ATtiny45, `CLK` being on `PB2` to have `INT0` on it. |
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The `DATA` line is multi-use. That is, `PB1` is connected both to the PS/2 data |
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line and to the 595's `SER`. This saves us a precious pin. |
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![ATtiny45](schema-t45.png) |
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The ATtiny 45 hooks everything together. `CE` comes from the z80 bus, see below. |
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![74xx595](schema-595.png) |
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This allows us to supply the z80 bus with data within its 375ns limits. `SRCLR` |
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is hooked to the `CE` line so that whenever a byte is read, the 595 is zeroed |
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out as fast as possible so that the z80 doesn't read "false doubles". |
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The 595, to have its `SRCLR` becoming effective, needs a `RCLK` trigger, which |
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doesn't happen immediately. It's the ATtiny45, in its `PCINT` interrupt, that |
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takes care of doing that trigger (as fast as possible). |
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![z80](schema-z80.png) |
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Our device is read only, on one port. That makes the "Chip Enable" (`CE`) |
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selection rather simple. In my design, I chose the IO port 8, so I inverted |
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`A3`. I chose a 40106 inverter to do that, do as you please for your own design. |
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I wanted to hook `CE` to a flip flop so that the MCU could relax a bit more |
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w.r.t. reacting to its `PB4` pin changes, but I didn't have NAND gates that are |
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fast enough in stock, so I went with this design. But otherwise, I would |
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probably have gone the flip-flop way. Seems more solid. |
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## Using the PS/2 interface |
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