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sms/spi: sample DO when CLK is high

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I was sampling DO at the wrong moment, so my input was always
one-off.
This commit is contained in:
Virgil Dupras 2020-11-08 10:24:36 -05:00
parent 2b8524d11e
commit 4b71f0a344
1 changed files with 1 additions and 1 deletions
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arch/z80/sms/blk/622
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@ -4,7 +4,7 @@
( send current bit to TRB, TR's output bit ) ( send current bit to TRB, TR's output bit )
DUP 7 I - RSHIFT 1 AND _TRB! DUP 7 I - RSHIFT 1 AND _TRB!
1 _THB! ( CLK hi ) 1 _THB! ( CLK hi )
0 _THB! ( CLK lo )
( read into rx ) SWAP 1 LSHIFT _D1@ ( tx rx<< x ) ( read into rx ) SWAP 1 LSHIFT _D1@ ( tx rx<< x )
0 _THB! ( CLK lo )
( out bit is the 6th ) 6 RSHIFT 1 AND OR ( out bit is the 6th ) 6 RSHIFT 1 AND OR
SWAP LOOP ( rx tx ) DROP ; SWAP LOOP ( rx tx ) DROP ;