sms: simplify and solidify ports-related drivers
Add _TRA!, _THA!, _TRB!, _THB! routines to easily handle those pins' value without stepping on other pins like the drivers previously did. For SDC driver, it's going to be important soon because it turns out that I can't get away with "always on" CS, so I'll need a scheme where it's important that TH/TR pins have stable values.
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@ -1,4 +1,4 @@
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Sega Master System Recipe
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Sega Master System Recipe
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602 VDP 610 PAD
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602 VDP 610 PAD
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620 KBD
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620 KBD 625 Ports
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@ -1,15 +1,7 @@
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CODE _status
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: _status
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A 0b11111101 LDri, ( TH output, unselected )
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1 _THA! ( output, high/unselected )
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PAD_CTLPORT OUTiA,
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_D1@ 0x3f AND ( low 6 bits are good )
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PAD_D1PORT INAi,
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0x3f ANDi, ( low 6 bits are good )
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H A LDrr, ( let's store them )
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( Start and A are returned when TH is selected, in bits 5 and
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( Start and A are returned when TH is selected, in bits 5 and
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4. Well get them, left-shift them and integrate them to B. )
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4. Well get them, left-shift them and integrate them to B. )
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A 0b11011101 LDri, ( TH output, selected )
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0 _THA! ( output, low/selected )
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PAD_CTLPORT OUTiA,
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_D1@ 0x30 AND 2 LSHIFT OR ;
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PAD_D1PORT INAi,
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0b00110000 ANDi,
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A SLA, A SLA, H ORr,
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PUSHA,
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;CODE
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@ -4,10 +4,9 @@
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is something to read. When the adapter is finished filling its
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is something to read. When the adapter is finished filling its
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'164 up, it resets the latch, which output's is connected to
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'164 up, it resets the latch, which output's is connected to
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TL. When the '164 is full, TL is low. Port A TL is bit 4 )
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TL. When the '164 is full, TL is low. Port A TL is bit 4 )
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0xdc PC@ 0x10 AND IF 0 EXIT ( nothing ) THEN
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_D1@ 0x10 AND IF 0 EXIT ( nothing ) THEN
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0x3f PC@ DROP 0b11011101 ( Port A TH output, low ) 0x3f PC!
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0 _THA! ( Port A TH output, low )
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0xdc PC@ ( bit 3:0 go in 3:0 ) 0x0f AND ( n )
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_D1@ ( bit 3:0 go in 3:0 ) 0x0f AND ( n )
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0b11111101 ( Port A TH output, high ) 0x3f PC!
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1 _THA! ( Port A TH output, high )
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0xdc PC@ ( bit 3:0 go in 7:4 ) 0x0f AND 4 LSHIFT OR ( n )
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_D1@ ( bit 3:0 go in 7:4 ) 0x0f AND 4 LSHIFT OR ( n )
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( Port A/B reset ) 0xff 0x3f PC!
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2 _THA! ( TH input ) ;
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;
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@ -1,11 +1,10 @@
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: (ps2kcB) ( for port B )
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: (ps2kcB) ( for port B )
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( Port B TL is bit 2 )
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( Port B TL is bit 2 )
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0xdd PC@ 0x04 AND IF 0 EXIT ( nothing ) THEN
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_D2@ 0x04 AND IF 0 EXIT ( nothing ) THEN
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0x3f PC@ DROP 0b01110111 ( Port B TH output, low ) 0x3f PC!
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0 _THB! ( Port B TH output, low )
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0xdc PC@ ( bit 7:6 go in 1:0 ) 6 RSHIFT ( n )
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_D1@ ( bit 7:6 go in 1:0 ) 6 RSHIFT ( n )
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0xdd PC@ ( bit 1:0 go in 3:2 ) 0x03 AND 2 LSHIFT OR ( n )
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_D2@ ( bit 1:0 go in 3:2 ) 0x03 AND 2 LSHIFT OR ( n )
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0b11110111 ( Port B TH output, high ) 0x3f PC!
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1 _THB! ( Port B TH output, high )
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0xdc PC@ ( bit 7:6 go in 5:4 ) 0xc0 AND 2 RSHIFT OR ( n )
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_D1@ ( bit 7:6 go in 5:4 ) 0xc0 AND 2 RSHIFT OR ( n )
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0xdd PC@ ( bit 1:0 go in 7:6 ) 0x03 AND 6 LSHIFT OR ( n )
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_D2@ ( bit 1:0 go in 7:6 ) 0x03 AND 6 LSHIFT OR ( n )
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( Port A/B reset ) 0xff 0x3f PC!
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2 _THB! ( TH input ) ;
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;
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@ -1,12 +1,10 @@
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: (spie) DROP ; ( always enabled )
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: (spie) DROP ; ( always enabled )
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: (spix) ( x -- x, for port B )
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: (spix) ( x -- x, for port B )
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0 SWAP ( rx tx ) 8 0 DO
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0 SWAP ( rx tx ) 8 0 DO
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( send bit 7 to bit 6, TR's output bit )
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( send current bit to TRB, TR's output bit )
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DUP 1 RSHIFT 0x40 AND ( rx tx bits ) 0x80 OR ( CLK hi )
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DUP 7 I - RSHIFT 1 AND _TRB!
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0x3f PC@ OR 0xf3 AND ( TH and TR output )
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1 _THB! ( CLK hi )
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DUP 0x3f PC! ( rx tx bits )
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0 _THB! ( CLK lo )
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( CLK low ) 0x7f AND 0x3f PC! ( rx tx )
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( read into rx ) SWAP 1 LSHIFT _D1@ ( tx rx<< x )
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( shift tx ) 1 LSHIFT ( rx tx<< )
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( read into rx ) SWAP 1 LSHIFT 0xdc PC@ ( tx<< rx<< x )
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( out bit is the 6th ) 6 RSHIFT 1 AND OR
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( out bit is the 6th ) 6 RSHIFT 1 AND OR
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SWAP LOOP ( rx tx ) DROP ;
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SWAP LOOP ( rx tx ) DROP ;
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15
arch/z80/sms/blk/625
Normal file
15
arch/z80/sms/blk/625
Normal file
@ -0,0 +1,15 @@
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( Routines for interacting with SMS controller ports.
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Requires CPORT_CTL, CPORT_D1 and CPORT_D2 to be defined.
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Will usually be 0x3f, 0xdc, 0xdd. )
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( mode -- set TR pin on mode a on:
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0= output low 1=output high 2=input )
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CODE _TRA! HL POP, chkPS, ( B0 -> B4, B1 -> B0 )
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L RR, RLA, RLA, RLA, RLA, L RR, RLA,
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0x11 ANDi, L A LDrr, CPORT_CTL INAi,
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0xee ANDi, L ORr, CPORT_CTL OUTiA,
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;CODE
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CODE _THA! HL POP, chkPS, ( B0 -> B5, B1 -> B1 )
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L RR, RLA, RLA, RLA, RLA, L RR, RLA, RLA,
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0x22 ANDi, L A LDrr, CPORT_CTL INAi,
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0xdd ANDi, L ORr, CPORT_CTL OUTiA,
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;CODE
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12
arch/z80/sms/blk/626
Normal file
12
arch/z80/sms/blk/626
Normal file
@ -0,0 +1,12 @@
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CODE _TRB! HL POP, chkPS, ( B0 -> B6, B1 -> B2 )
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L RR, RLA, RLA, RLA, RLA, L RR, RLA, RLA, RLA,
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0x44 ANDi, L A LDrr, CPORT_CTL INAi,
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0xbb ANDi, L ORr, CPORT_CTL OUTiA,
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;CODE
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CODE _THB! HL POP, chkPS, ( B0 -> B7, B1 -> B3 )
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L RR, RLA, RLA, RLA, RLA, L RR, RLA, RLA, RLA, RLA,
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0x88 ANDi, L A LDrr, CPORT_CTL INAi,
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0x77 ANDi, L ORr, CPORT_CTL OUTiA,
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;CODE
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CODE _D1@ CPORT_D1 INAi, PUSHA, ;CODE
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CODE _D2@ CPORT_D2 INAi, PUSHA, ;CODE
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@ -10,8 +10,9 @@ SYSVARS 0x70 + CONSTANT VDP_MEM
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32 CONSTANT VDP_COLS
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32 CONSTANT VDP_COLS
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24 CONSTANT VDP_ROWS
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24 CONSTANT VDP_ROWS
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SYSVARS 0x72 + CONSTANT PAD_MEM
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SYSVARS 0x72 + CONSTANT PAD_MEM
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0x3f CONSTANT PAD_CTLPORT
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0x3f CONSTANT CPORT_CTL
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0xdc CONSTANT PAD_D1PORT
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0xdc CONSTANT CPORT_D1
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0xdd CONSTANT CPORT_D2
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5 LOAD ( z80 assembler )
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5 LOAD ( z80 assembler )
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: ZFILL, ( u ) 0 DO 0 A, LOOP ;
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: ZFILL, ( u ) 0 DO 0 A, LOOP ;
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262 LOAD ( xcomp )
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262 LOAD ( xcomp )
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@ -28,6 +29,7 @@ CURRENT @ XCURRENT !
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353 LOAD ( xcomp core low )
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353 LOAD ( xcomp core low )
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CREATE ~FNT CPFNT7x7
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CREATE ~FNT CPFNT7x7
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603 608 LOADR ( VDP )
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603 608 LOADR ( VDP )
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625 626 LOADR ( SMS ports )
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612 617 LOADR ( PAD )
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612 617 LOADR ( PAD )
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390 LOAD ( xcomp core high )
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390 LOAD ( xcomp core high )
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(entry) _
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(entry) _
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41
arch/z80/sms/xcompkbd.fs
Normal file
41
arch/z80/sms/xcompkbd.fs
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@ -0,0 +1,41 @@
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( xcomp for a SMS with PS/2 keyboard on port A )
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( 8K of onboard RAM )
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0xdd00 CONSTANT RS_ADDR
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( Memory register at the end of RAM. Must not overwrite )
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0xddca CONSTANT PS_ADDR
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RS_ADDR 0x80 - CONSTANT SYSVARS
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0xc000 CONSTANT HERESTART
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SYSVARS 0x70 + CONSTANT VDP_MEM
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0xbf CONSTANT VDP_CTLPORT
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0xbe CONSTANT VDP_DATAPORT
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32 CONSTANT VDP_COLS
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24 CONSTANT VDP_ROWS
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SYSVARS 0x72 + CONSTANT PS2_MEM
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0x3f CONSTANT CPORT_CTL
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0xdc CONSTANT CPORT_D1
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0xdd CONSTANT CPORT_D2
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5 LOAD ( z80 assembler )
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: ZFILL, ( u ) 0 DO 0 A, LOOP ;
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262 LOAD ( xcomp )
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524 LOAD ( font compiler )
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282 LOAD ( boot.z80.decl )
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270 LOAD ( xcomp overrides )
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DI, 0x100 JP, 0x62 ZFILL, ( 0x66 )
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RETN, 0x98 ZFILL, ( 0x100 )
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( All set, carry on! )
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CURRENT @ XCURRENT !
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0x100 BIN( !
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283 335 LOADR ( boot.z80 )
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353 LOAD ( xcomp core low )
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CREATE ~FNT CPFNT7x7
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603 608 LOADR ( VDP )
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625 626 LOADR ( SMS ports )
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620 LOAD ( PAD ) : (ps2kc) (ps2kcA) ; 411 414 LOADR
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390 LOAD ( xcomp core high )
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(entry) _
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( Update LATEST )
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PC ORG @ 8 + !
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," VDP$ PS2$ (im1) " EOT,
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ORG @ 0x100 - 256 /MOD 2 PC! 2 PC!
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H@ 256 /MOD 2 PC! 2 PC!
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44
arch/z80/sms/xcompsdc.fs
Normal file
44
arch/z80/sms/xcompsdc.fs
Normal file
@ -0,0 +1,44 @@
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( xcomp for a SMS with PS/2 keyboard on port A and SPI relay
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on port B, with SD card attached )
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( 8K of onboard RAM )
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0xdd00 CONSTANT RS_ADDR
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( Memory register at the end of RAM. Must not overwrite )
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0xddca CONSTANT PS_ADDR
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RS_ADDR 0x80 - CONSTANT SYSVARS
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0xc000 CONSTANT HERESTART
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SYSVARS 0x70 + CONSTANT VDP_MEM
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0xbf CONSTANT VDP_CTLPORT
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0xbe CONSTANT VDP_DATAPORT
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32 CONSTANT VDP_COLS
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24 CONSTANT VDP_ROWS
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SYSVARS 0x72 + CONSTANT PS2_MEM
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0x3f CONSTANT CPORT_CTL
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0xdc CONSTANT CPORT_D1
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0xdd CONSTANT CPORT_D2
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5 LOAD ( z80 assembler )
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: ZFILL, ( u ) 0 DO 0 A, LOOP ;
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262 LOAD ( xcomp )
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524 LOAD ( font compiler )
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282 LOAD ( boot.z80.decl )
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270 LOAD ( xcomp overrides )
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DI, 0x100 JP, 0x62 ZFILL, ( 0x66 )
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RETN, 0x98 ZFILL, ( 0x100 )
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( All set, carry on! )
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CURRENT @ XCURRENT !
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0x100 BIN( !
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283 335 LOADR ( boot.z80 )
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353 LOAD ( xcomp core low )
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CREATE ~FNT CPFNT7x7
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603 608 LOADR ( VDP )
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625 626 LOADR ( SMS ports )
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620 LOAD ( PAD ) : (ps2kc) (ps2kcA) ; 411 414 LOADR
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622 LOAD ( SPI )
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1 CONSTANT SDC_DEVID 423 436 LOADR ( SDC )
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390 LOAD ( xcomp core high )
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(entry) _
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( Update LATEST )
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PC ORG @ 8 + !
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," VDP$ PS2$ BLK$ (im1) " EOT,
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ORG @ 0x100 - 256 /MOD 2 PC! 2 PC!
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H@ 256 /MOD 2 PC! 2 PC!
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@ -76,6 +76,11 @@ static uint8_t iord_kbd()
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return kbd_rd(&kbd);
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return kbd_rd(&kbd);
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}
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}
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static uint8_t iord_ports_ctl()
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{
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return ports_ctl_rd(&ports);
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}
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static void iowr_vdp_cmd(uint8_t val)
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static void iowr_vdp_cmd(uint8_t val)
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{
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{
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vdp_cmd_wr(&vdp, val);
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vdp_cmd_wr(&vdp, val);
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@ -357,7 +362,7 @@ int main(int argc, char *argv[])
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m->iord[VDP_DATA_PORT] = iord_vdp_data;
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m->iord[VDP_DATA_PORT] = iord_vdp_data;
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m->iord[PORTS_IO1_PORT] = iord_ports_io1;
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m->iord[PORTS_IO1_PORT] = iord_ports_io1;
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m->iord[PORTS_IO2_PORT] = iord_ports_io2;
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m->iord[PORTS_IO2_PORT] = iord_ports_io2;
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m->iord[PORTS_CTL_PORT] = iord_noop;
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m->iord[PORTS_CTL_PORT] = iord_ports_ctl;
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m->iowr[VDP_CMD_PORT] = iowr_vdp_cmd;
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m->iowr[VDP_CMD_PORT] = iowr_vdp_cmd;
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m->iowr[VDP_DATA_PORT] = iowr_vdp_data;
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m->iowr[VDP_DATA_PORT] = iowr_vdp_data;
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m->iowr[PORTS_CTL_PORT] = iowr_ports_ctl;
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m->iowr[PORTS_CTL_PORT] = iowr_ports_ctl;
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