By default, allocate about 0x100 bytes for PSP+RSP

During "make updatebootstrap", we use less than 0x20 bytes on the
PSP side and less than 0x40 bytes on the RSP one. 0x100 bytes ought
to be enough for anybody.
This commit is contained in:
Virgil Dupras 2020-05-14 18:41:09 -04:00
parent bf289b0a67
commit 87b51a6261
8 changed files with 12 additions and 15 deletions

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@ -1,5 +1,5 @@
0x8000 CONSTANT RAMSTART 0x8000 CONSTANT RAMSTART
0xf000 CONSTANT RS_ADDR 0xfffa CONSTANT PS_ADDR 0xff00 CONSTANT RS_ADDR 0xfffa CONSTANT PS_ADDR
0x80 CONSTANT ACIA_CTL 0x81 CONSTANT ACIA_IO 0x80 CONSTANT ACIA_CTL 0x81 CONSTANT ACIA_IO
4 CONSTANT SDC_SPI 4 CONSTANT SDC_SPI
5 CONSTANT SDC_CSLOW 6 CONSTANT SDC_CSHIGH 5 CONSTANT SDC_CSLOW 6 CONSTANT SDC_CSHIGH

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@ -53,6 +53,7 @@ Machine* emul_init()
memset(m.mem, 0, 0x10000); memset(m.mem, 0, 0x10000);
m.ramstart = 0; m.ramstart = 0;
m.minsp = 0xffff; m.minsp = 0xffff;
m.maxix = 0;
for (int i=0; i<0x100; i++) { for (int i=0; i<0x100; i++) {
m.iord[i] = NULL; m.iord[i] = NULL;
m.iowr[i] = NULL; m.iowr[i] = NULL;
@ -74,6 +75,9 @@ bool emul_step()
if (newsp != 0 && newsp < m.minsp) { if (newsp != 0 && newsp < m.minsp) {
m.minsp = newsp; m.minsp = newsp;
} }
if (m.cpu.R1.wr.IX > m.maxix) {
m.maxix = m.cpu.R1.wr.IX;
}
return true; return true;
} else { } else {
return false; return false;
@ -116,4 +120,5 @@ void emul_memdump()
void emul_printdebug() void emul_printdebug()
{ {
fprintf(stderr, "Min SP: %04x\n", m.minsp); fprintf(stderr, "Min SP: %04x\n", m.minsp);
fprintf(stderr, "Max IX: %04x\n", m.maxix);
} }

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@ -14,6 +14,8 @@ typedef struct {
ushort ramstart; ushort ramstart;
// The minimum value reached by SP at any point during execution. // The minimum value reached by SP at any point during execution.
ushort minsp; ushort minsp;
// same principle for IX
ushort maxix;
// Array of 0x100 function pointers to IO read and write routines. Leave to // Array of 0x100 function pointers to IO read and write routines. Leave to
// NULL when IO port is unhandled. // NULL when IO port is unhandled.
IORD iord[0x100]; IORD iord[0x100];

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@ -20,11 +20,6 @@ trouble of compiling defs to binary.
*/ */
// When DEBUG is set, stage1 is a core-less forth that works interactively.
// Useful for... debugging!
// By the way: there's a double-echo in stagedbg. It's normal. Don't panic.
//#define DEBUG
#define RAMSTART 0 #define RAMSTART 0
#define STDIO_PORT 0x00 #define STDIO_PORT 0x00
// To know which part of RAM to dump, we listen to port 2, which at the end of // To know which part of RAM to dump, we listen to port 2, which at the end of
@ -56,10 +51,6 @@ static uint8_t iord_stdio()
static void iowr_stdio(uint8_t val) static void iowr_stdio(uint8_t val)
{ {
// we don't output stdout in stage0 // we don't output stdout in stage0
#ifdef DEBUG
// ... unless we're in DEBUG mode!
putchar(val);
#endif
} }
static void iowr_here(uint8_t val) static void iowr_here(uint8_t val)
@ -101,12 +92,11 @@ int main(int argc, char *argv[])
while (running && emul_step()); while (running && emul_step());
#ifndef DEBUG
// We're done, now let's spit dict data // We're done, now let's spit dict data
for (int i=start_here; i<end_here; i++) { for (int i=start_here; i<end_here; i++) {
putchar(m->mem[i]); putchar(m->mem[i]);
} }
#endif emul_printdebug();
return 0; return 0;
} }

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@ -1,5 +1,5 @@
0xe800 CONSTANT RAMSTART 0xe800 CONSTANT RAMSTART
0xf000 CONSTANT RS_ADDR 0xff00 CONSTANT RS_ADDR
0xfffa CONSTANT PS_ADDR 0xfffa CONSTANT PS_ADDR
212 LOAD ( z80 assembler ) 212 LOAD ( z80 assembler )
262 LOAD ( xcomp ) 262 LOAD ( xcomp )

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@ -1,5 +1,5 @@
0x8000 CONSTANT RAMSTART 0x8000 CONSTANT RAMSTART
0xb000 CONSTANT RS_ADDR 0xbf00 CONSTANT RS_ADDR
0xbffa CONSTANT PS_ADDR 0xbffa CONSTANT PS_ADDR
RAMSTART 0x70 + CONSTANT LCD_MEM RAMSTART 0x70 + CONSTANT LCD_MEM
RAMSTART 0x72 + CONSTANT KBD_MEM RAMSTART 0x72 + CONSTANT KBD_MEM

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@ -1,4 +1,4 @@
0xf000 CONSTANT RS_ADDR 0xff00 CONSTANT RS_ADDR
0xfffa CONSTANT PS_ADDR 0xfffa CONSTANT PS_ADDR
RS_ADDR 0x80 - CONSTANT RAMSTART RS_ADDR 0x80 - CONSTANT RAMSTART
212 LOAD ( z80 assembler ) 212 LOAD ( z80 assembler )