avra: add global constants
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Virgil Dupras
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blk/672
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8
blk/672
Normal file
@ -0,0 +1,8 @@
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( Constant common to all AVR models )
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: R0 0 ; : R1 1 ; : R2 2 ; : R3 3 ; : R4 4 ; : R5 5 ; : R6 6 ;
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: R7 7 ; : R8 8 ; : R9 9 ; : R10 10 ; : R11 11 ; : R12 12 ;
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: R13 13 ; : R14 14 ; : R15 15 ; : R16 16 ; : R17 17 ;
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: R18 18 ; : R19 19 ; : R20 20 ; : R21 21 ; : R22 22 ;
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: R24 24 ; : R25 25 ; : R26 26 ; : R27 27 ; : R28 28 ;
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: R29 29 ; : R30 30 ; : R31 31 ; : XL R26 ; : XH R27 ;
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: YL R28 ; : YH R29 ; : ZL R30 ; : ZH R31 ;
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@ -67,31 +67,31 @@ SET,
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RETI,
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L1 ' RJMP FLBL! ( main )
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16 RAMEND 0xff AND LDI,
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SPL 16 OUT,
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16 RAMEND 8 RSHIFT LDI,
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SPH 16 OUT,
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R16 RAMEND 0xff AND LDI,
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SPL R16 OUT,
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R16 RAMEND 8 RSHIFT LDI,
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SPH R16 OUT,
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( init variables )
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18 CLR,
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GPIOR0 18 OUT,
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R18 CLR,
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GPIOR0 R18 OUT,
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( Setup int0
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INT0, falling edge )
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16 0x02 ( ISC01 ) LDI,
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MCUCR 16 OUT,
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R16 0x02 ( ISC01 ) LDI,
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MCUCR R16 OUT,
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( Enable INT0 )
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16 0x40 ( INT0 ) LDI,
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GIMSK 16 OUT,
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R16 0x40 ( INT0 ) LDI,
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GIMSK R16 OUT,
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( Setup buffer )
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29 ( YH ) CLR,
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28 ( YL ) SRAM_START 0xff AND LDI,
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31 ( ZH ) CLR,
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30 ( ZL ) SRAM_START 0xff AND LDI,
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YH CLR,
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YL SRAM_START 0xff AND LDI,
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ZH CLR,
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ZL SRAM_START 0xff AND LDI,
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( Setup timer. We use the timer to clear up "processbit"
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registers after 100us without a clock. This allows us to start
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the next frame in a fresh state. at 1MHZ, no prescaling is
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necessary. Each TCNT0 tick is already 1us long. )
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16 0x01 ( CS00 ) LDI, ( no prescaler )
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TCCR0B 16 OUT,
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R16 0x01 ( CS00 ) LDI, ( no prescaler )
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TCCR0B R16 OUT,
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( init DDRB )
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DDRB CP SBI,
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PORTB LR CBI,
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@ -101,20 +101,20 @@ SEI,
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L1 LBL! ( loop )
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L2 FLBL, ( BRTS processbit. flag T set? we have a bit to
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process )
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28 ( YL ) 30 ( ZL ) CP, ( if YL == ZL, buf is empty )
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YL ZL CP, ( if YL == ZL, buf is empty )
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L3 FLBL, ( BRNE sendTo164. YL != ZL? buf has data )
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( nothing to do. Before looping, let's check if our
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communication timer overflowed. )
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16 TIFR IN,
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16 1 ( TOV0 ) SBRC,
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R16 TIFR IN,
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R16 1 ( TOV0 ) SBRC,
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L4 FLBL, ( RJMP processbitReset, timer0 overflow? reset )
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( Nothing to do for real. )
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L1 ' RJMP LBL, ( loop )
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( Process the data bit received in INT0 handler. )
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L2 ' BRTS FLBL! ( processbit )
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19 GPIOR0 IN, ( backup GPIOR0 before we reset T )
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19 0x1 ANDI, ( only keep the first flag )
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R19 GPIOR0 IN, ( backup GPIOR0 before we reset T )
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R19 0x1 ANDI, ( only keep the first flag )
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GPIOR0 0 CBI,
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CLT, ( ready to receive another bit )
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@ -122,31 +122,31 @@ CLT, ( ready to receive another bit )
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L2 FLBL, ( RCALL resetTimer )
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( Which step are we at? )
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18 TST,
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R18 TST,
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L5 FLBL, ( BREQ processbits0 )
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18 1 CPI,
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R18 1 CPI,
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L6 FLBL, ( BREQ processbits1 )
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18 2 CPI,
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R18 2 CPI,
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L7 FLBL, ( BREQ processbits2 )
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( step 3: stop bit )
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18 CLR, ( happens in all cases )
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R18 CLR, ( happens in all cases )
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( DATA has to be set )
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19 TST, ( was DATA set? )
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R19 TST, ( was DATA set? )
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L1 ' BREQ LBL, ( loop, not set? error, don't push to buf )
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( push r17 to the buffer )
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Y+ 17 ST,
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Y+ R17 ST,
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L8 FLBL, ( RCALL checkBoundsY )
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L1 ' RJMP LBL,
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L5 ' BREQ FLBL! ( processbits0 )
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( step 0 - start bit )
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( DATA has to be cleared )
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19 TST, ( was DATA set? )
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R19 TST, ( was DATA set? )
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L1 ' BRNE LBL, ( loop. set? error. no need to do anything. keep
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r18 as-is. )
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( DATA is cleared. prepare r17 and r18 for step 1 )
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18 INC,
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17 0x80 LDI,
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R18 INC,
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R17 0x80 LDI,
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L1 ' RJMP LBL, ( loop )
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L6 ' BREQ FLBL! ( processbits1 )
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@ -154,35 +154,35 @@ L6 ' BREQ FLBL! ( processbits1 )
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We're about to rotate the carry flag into r17. Let's set it
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first depending on whether DATA is set. )
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CLC,
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19 0 SBRC, ( skip if DATA is cleared )
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R19 0 SBRC, ( skip if DATA is cleared )
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SEC,
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( Carry flag is set )
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17 ROR,
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R17 ROR,
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( Good. now, are we finished rotating? If carry flag is set,
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it means that we've rotated in 8 bits. )
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L1 ' BRCC LBL, ( loop )
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( We're finished, go to step 2 )
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18 INC,
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R18 INC,
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L1 ' RJMP LBL, ( loop )
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L7 ' BREQ FLBL! ( processbits2 )
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( step 2 - parity bit )
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1 19 MOV,
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19 17 MOV,
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R1 R19 MOV,
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R19 R17 MOV,
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L5 FLBL, ( RCALL checkParity )
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1 16 CP,
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R1 R16 CP,
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L6 FLBL, ( BRNE processBitError, r1 != r16? wrong parity )
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18 INC,
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R18 INC,
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L1 ' RJMP LBL, ( loop )
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L6 ' BRNE FLBL! ( processBitError )
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18 CLR,
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19 0xfe LDI,
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R18 CLR,
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R19 0xfe LDI,
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L6 FLBL, ( RCALL sendToPS2 )
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L1 ' RJMP LBL, ( loop )
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L4 ' RJMP FLBL! ( processbitReset )
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18 CLR,
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R18 CLR,
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L4 FLBL, ( RCALL resetTimer )
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L1 ' RJMP LBL, ( loop )
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@ -197,19 +197,19 @@ L1 ' RJMP LBL, ( loop, even if we have something in the
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and processing it might mess things up. )
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CLI,
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DDRB DATA SBI,
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20 Z+ LD,
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R20 Z+ LD,
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L3 FLBL, ( RCALL checkBoundsZ )
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16 8 LDI,
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R16 R8 LDI,
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BEGIN,
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PORTB DATA CBI,
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20 7 SBRC, ( if leftmost bit isn't cleared, set DATA high )
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R20 7 SBRC, ( if leftmost bit isn't cleared, set DATA high )
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PORTB DATA SBI,
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( toggle CP )
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PORTB CP CBI,
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20 LSL,
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R20 LSL,
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PORTB CP SBI,
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16 DEC,
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R16 DEC,
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' BRNE AGAIN?, ( not zero yet? loop )
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( release PS/2 )
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DDRB DATA CBI,
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@ -220,10 +220,10 @@ PORTB LR CBI,
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L1 ' RJMP LBL, ( loop )
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L2 ' RCALL FLBL! L4 ' RCALL FLBL! L2 LBL! ( resetTimer )
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16 TIMER_INITVAL LDI,
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TCNT0 16 OUT,
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16 0x02 ( TOV0 ) LDI,
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TIFR 16 OUT,
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R16 TIMER_INITVAL LDI,
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TCNT0 R16 OUT,
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R16 0x02 ( TOV0 ) LDI,
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TIFR R16 OUT,
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RET,
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L6 ' RCALL FLBL! ( sendToPS2 )
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@ -237,8 +237,8 @@ L2 ' RCALL LBL, ( resetTimer )
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( Wait until the timer overflows )
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BEGIN,
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16 TIFR IN,
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16 1 ( TOV0 ) SBRS,
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R16 TIFR IN,
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R16 1 ( TOV0 ) SBRS,
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AGAIN,
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( Good, 100us passed. )
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( Pull Data low, that's our start bit. )
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@ -251,31 +251,31 @@ DDRB DATA SBI,
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DDRB CLK CBI, ( Should be starting high now. )
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( We will do the next loop 8 times )
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16 8 LDI,
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R16 8 LDI,
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( Let's remember initial r19 for parity )
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1 19 MOV,
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R1 R19 MOV,
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BEGIN,
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( Wait for CLK to go low )
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BEGIN, PINB CLK SBIC, AGAIN,
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( set up DATA )
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PORTB DATA CBI,
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19 0 SBRC, ( skip if LSB is clear )
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R19 0 SBRC, ( skip if LSB is clear )
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PORTB DATA SBI,
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19 LSR,
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R19 LSR,
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( Wait for CLK to go high )
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BEGIN, PINB CLK SBIS, AGAIN,
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16 DEC,
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' BRNE AGAIN?, ( not zero? loop )
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( Data was sent, CLK is high. Let's send parity )
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19 1 MOV, ( recall saved value )
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R19 R1 MOV, ( recall saved value )
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L6 FLBL, ( RCALL checkParity )
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( Wait for CLK to go low )
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BEGIN, PINB CLK SBIC, AGAIN,
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( set parity bit )
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PORTB DATA CBI,
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16 0 SBRC, ( parity bit in r16 )
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R16 0 SBRC, ( parity bit in r16 )
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PORTB DATA SBI,
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( Wait for CLK to go high )
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BEGIN, PINB CLK SBIS, AGAIN,
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@ -296,30 +296,30 @@ RET,
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L8 ' RCALL FLBL! ( checkBoundsY )
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( Check that Y is within bounds, reset to SRAM_START if not. )
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28 ( YL ) TST,
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YL TST,
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IF, RET, ( not zero, nothing to do ) THEN,
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( YL is zero. Reset Z )
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29 ( YH ) CLR,
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28 ( YL ) SRAM_START 0xff AND LDI,
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YH CLR,
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YL SRAM_START 0xff AND LDI,
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RET,
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L3 ' RCALL FLBL! ( checkBoundsZ )
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( Check that Z is within bounds, reset to SRAM_START if not. )
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30 ( ZL ) TST,
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ZL TST,
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IF, RET, ( not zero, nothing to do ) THEN,
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( ZL is zero. Reset Z )
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31 ( ZH ) CLR,
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30 ( ZL ) SRAM_START 0xff AND LDI,
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ZH CLR,
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ZL SRAM_START 0xff AND LDI,
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RET,
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L5 ' RCALL FLBL! L6 ' RCALL FLBL! ( checkParity )
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( Counts the number of 1s in r19 and set r16 to 1 if there's an
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even number of 1s, 0 if they're odd. )
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16 1 LDI,
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R16 1 LDI,
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BEGIN,
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19 LSR,
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' BRCC SKIP, 16 INC, ( carry set? we had a 1 ) TO,
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19 TST, ( is r19 zero yet? )
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R19 LSR,
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' BRCC SKIP, R16 INC, ( carry set? we had a 1 ) TO,
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R19 TST, ( is r19 zero yet? )
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' BRNE AGAIN?, ( no? loop )
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16 0x1 ANDI,
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R16 0x1 ANDI,
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RET,
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