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@@ -8,6 +8,17 @@ |
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; with PD7:2 for bits 7:2 and PB1:0 for bits 1:0 (PD1 and PD0 are used for |
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; UART). |
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; |
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; *** Timing, matching and CE *** |
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; |
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; A lot of trial-and-errors went into those NOPs being place to give time for |
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; latching. All these timing are well, well above maximums given in the specs, |
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; but when I wasn't going well, well above those specs, I was experiencing |
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; read/write errors. It seems we live in an imperfect world! |
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; |
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; I'm also not sure, in "writedata", whether toggling CE along with WE is |
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; actually needed, but until I did, I was experiencing random write failures. |
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; So, we end up with this... |
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; |
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; *** Register Usage *** |
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; |
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; r0: holds whether last received char was tty-escaped (0 = no, 1=yes) |
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@@ -92,6 +103,10 @@ sendaddr: |
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; send r20 to EEPROM's I/O7:0 through PD7:2 and PB1:0 |
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writedata: |
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cbi PORTB, FLCE |
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; addr is latched on WE falling edge |
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cbi PORTB, FLWE |
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; send bits 7:2 |
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mov r16, r20 |
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andi r16, 0xfc |
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@@ -106,49 +121,59 @@ writedata: |
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andi r17, 0xfc |
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or r16, r17 |
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out PORTB, r16 |
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; data is latched on rising edge |
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sbi PORTB, FLWE |
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sbi PORTB, FLCE |
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nop ; Give the AT28 time to latch |
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nop |
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nop |
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ret |
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; push r20 to the rom and increase the memory counter |
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pushdata: |
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nextaddr: |
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; first, set up addr |
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mov r23, r21 |
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rcall sendaddr |
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mov r23, r22 |
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rcall sendaddr |
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inc r22 |
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brne pushdata_0 ; no overflow? skip |
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brne nextaddr_0 ; no overflow? skip |
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inc r21 |
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pushdata_0: |
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; addr is latched on WE falling edge |
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cbi PORTB, FLWE |
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; now, lets set up data. Plenty enough instructions to ensure a 100ns |
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; minimum delay. |
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rcall writedata |
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; data is latched on rising edge |
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sbi PORTB, FLWE |
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nextaddr_0: |
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ret |
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; wait until I/O7 stops toggling |
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waitio7: |
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cbi PORTB, FLCE |
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cbi PORTB, FLOE |
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nop ; Give the AT28 time to latch |
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nop |
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nop |
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in r16, PIND |
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sbi PORTB, FLOE |
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sbi PORTB, FLCE |
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andi r16, 0xfc |
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cbi PORTB, FLCE |
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cbi PORTB, FLOE |
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nop ; Give the AT28 time to latch |
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nop |
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nop |
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in r17, PIND |
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sbi PORTB, FLOE |
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sbi PORTB, FLCE |
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andi r17, 0xfc |
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cp r16, r17 |
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brne waitio7 |
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ret |
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; read EEPROM's I/O7:0 through PD7:2 and PB1:0 and put result in r20. |
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; read EEPROM's I/O7:0 through PD7:2 and PB1:0 into r20 |
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readdata: |
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cbi PORTB, FLCE |
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cbi PORTB, FLOE |
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nop ; Give the AT28 time to latch |
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nop |
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nop |
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; read bits 7:2 |
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in r20, PIND |
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andi r20, 0xfc |
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@@ -157,13 +182,14 @@ readdata: |
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andi r16, 0x03 |
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or r20, r16 |
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sbi PORTB, FLOE |
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sbi PORTB, FLCE |
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ret |
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; Set PD7:2 and PB1:0 to output |
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ioout: |
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ldi r16, 0xfc ; PD7:2 |
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out DDRD, r16 |
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ldi r16, 0x3f ; PB5:0 (WE, OE and CE too) |
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ldi r16, 0x3f ; PB5:0 (CP, WE, OE and CE too) |
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out DDRB, r16 |
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ret |
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@@ -181,11 +207,9 @@ main: |
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ldi r16, high(RAMEND) |
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out SPH, r16 |
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; We begin with WE and OE disabled (high), but CE stays enabled (low) |
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; the whole time. |
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sbi PORTB, FLWE |
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sbi PORTB, FLOE |
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cbi PORTB, FLCE |
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sbi PORTB, FLCE |
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; Clear counters and flags |
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clr r0 |
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@@ -204,7 +228,8 @@ main: |
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loop: |
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rcall uartrd |
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rcall ioout |
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rcall pushdata |
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rcall nextaddr |
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rcall writedata |
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rcall ioin |
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rcall waitio7 |
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rcall readdata |
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