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collapseos/emul/8086/cpu.c

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  1. /* Extracted from the Fake86 project and heavily modified to run within

  2.    the Collapse OS project with its simple needs.

  3. */

  4. /*

  5.   Fake86: A portable, open-source 8086 PC emulator.

  6.   Copyright (C)2010-2013 Mike Chambers

  7. 

  8.   This program is free software; you can redistribute it and/or

  9.   modify it under the terms of the GNU General Public License

  10.   as published by the Free Software Foundation; either version 2

  11.   of the License, or (at your option) any later version.

  12. 

  13.   This program is distributed in the hope that it will be useful,

  14.   but WITHOUT ANY WARRANTY; without even the implied warranty of

  15.   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

  16.   GNU General Public License for more details.

  17. 

  18.   You should have received a copy of the GNU General Public License

  19.   along with this program; if not, write to the Free Software

  20.   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

  21. */

  22. 

  23. #include <stdint.h>

  24. #include <stdio.h>

  25. #include "cpu.h"

  26. 

  27. #define StepIP(x)	ip += x

  28. #define signext(value)	(int16_t)(int8_t)(value)

  29. #define signext32(value)	(int32_t)(int16_t)(value)

  30. #define getsegreg(regid)	segregs[regid]

  31. #define putsegreg(regid, writeval)	segregs[regid] = writeval

  32. // Warning: those macros below *can't* be called with reg*l and reg*h

  33. #define getreg8(regid)	regs.byteregs[byteregtable[regid]]

  34. #define putreg8(regid, writeval)	regs.byteregs[byteregtable[regid]] = writeval

  35. 

  36. uint8_t byteregtable[8] = { regal, regcl, regdl, regbl, regah, regch, regdh, regbh };

  37. 

  38. static const uint8_t parity[0x100] = {

  39. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  40. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  41. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  42. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  43. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  44. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  45. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  46. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1

  47. };

  48. 

  49. uint8_t	RAM[0x100000];

  50. INTHOOK INTHOOKS[0x100] = {0};

  51. uint8_t	opcode, segoverride, reptype, hltstate = 0;

  52. uint16_t segregs[4], ip, useseg, oldsp;

  53. uint8_t	tempcf, cf, pf, af, zf, sf, tf, ifl, df, of, mode, reg, rm;

  54. uint16_t oper1, oper2, res16, disp16, temp16, stacksize, frametemp;

  55. uint8_t	oper1b, oper2b, res8, disp8, nestlev, addrbyte;

  56. uint32_t temp1, temp2, temp3, ea;

  57. 

  58. union _bytewordregs_ regs;

  59. 

  60. uint8_t	portram[0x10000];

  61. 

  62. void intcall86(uint8_t intnum);

  63. 

  64. static void	portout (uint16_t portnum, uint8_t value) {}

  65. static void	portout16 (uint16_t portnum, uint16_t value) {}

  66. static uint8_t	portin (uint16_t portnum) { return 0; }

  67. static uint16_t portin16 (uint16_t portnum) { return 0; }

  68. 

  69. void write86 (uint32_t addr32, uint8_t value) {

  70.     RAM[addr32 & 0xFFFFF] = value;

  71. }

  72. 

  73. void writew86 (uint32_t addr32, uint16_t value) {

  74. 	write86(addr32, (uint8_t) value);

  75. 	write86(addr32 + 1, (uint8_t) (value >> 8) );

  76. }

  77. 

  78. uint8_t read86 (uint32_t addr32) {

  79. 	addr32 &= 0xFFFFF;

  80. 	return (RAM[addr32]);

  81. }

  82. 

  83. uint16_t readw86 (uint32_t addr32) {

  84. 	return ( (uint16_t) read86 (addr32) | (uint16_t) (read86 (addr32 + 1) << 8) );

  85. }

  86. 

  87. static void flag_szp8 (uint8_t value) {

  88. 	if (!value) {

  89. 			zf = 1;

  90. 		}

  91. 	else {

  92. 			zf = 0;	/* set or clear zero flag */

  93. 		}

  94. 

  95. 	if (value & 0x80) {

  96. 			sf = 1;

  97. 		}

  98. 	else {

  99. 			sf = 0;	/* set or clear sign flag */

  100. 		}

  101. 

  102. 	pf = parity[value]; /* retrieve parity state from lookup table */

  103. }

  104. 

  105. static void flag_szp16 (uint16_t value) {

  106. 	if (!value) {

  107. 			zf = 1;

  108. 		}

  109. 	else {

  110. 			zf = 0;	/* set or clear zero flag */

  111. 		}

  112. 

  113. 	if (value & 0x8000) {

  114. 			sf = 1;

  115. 		}

  116. 	else {

  117. 			sf = 0;	/* set or clear sign flag */

  118. 		}

  119. 

  120. 	pf = parity[value & 255];	/* retrieve parity state from lookup table */

  121. }

  122. 

  123. static void flag_log8 (uint8_t value) {

  124. 	flag_szp8 (value);

  125. 	cf = 0;

  126. 	of = 0; /* bitwise logic ops always clear carry and overflow */

  127. }

  128. 

  129. static void flag_log16 (uint16_t value) {

  130. 	flag_szp16 (value);

  131. 	cf = 0;

  132. 	of = 0; /* bitwise logic ops always clear carry and overflow */

  133. }

  134. 

  135. static void flag_adc8 (uint8_t v1, uint8_t v2, uint8_t v3) {

  136. 

  137. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  138. 	uint16_t	dst;

  139. 

  140. 	dst = (uint16_t) v1 + (uint16_t) v2 + (uint16_t) v3;

  141. 	flag_szp8 ( (uint8_t) dst);

  142. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x80) == 0x80) {

  143. 			of = 1;

  144. 		}

  145. 	else {

  146. 			of = 0; /* set or clear overflow flag */

  147. 		}

  148. 

  149. 	if (dst & 0xFF00) {

  150. 			cf = 1;

  151. 		}

  152. 	else {

  153. 			cf = 0; /* set or clear carry flag */

  154. 		}

  155. 

  156. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  157. 			af = 1;

  158. 		}

  159. 	else {

  160. 			af = 0; /* set or clear auxilliary flag */

  161. 		}

  162. }

  163. 

  164. static void flag_adc16 (uint16_t v1, uint16_t v2, uint16_t v3) {

  165. 

  166. 	uint32_t	dst;

  167. 

  168. 	dst = (uint32_t) v1 + (uint32_t) v2 + (uint32_t) v3;

  169. 	flag_szp16 ( (uint16_t) dst);

  170. 	if ( ( ( (dst ^ v1) & (dst ^ v2) ) & 0x8000) == 0x8000) {

  171. 			of = 1;

  172. 		}

  173. 	else {

  174. 			of = 0;

  175. 		}

  176. 

  177. 	if (dst & 0xFFFF0000) {

  178. 			cf = 1;

  179. 		}

  180. 	else {

  181. 			cf = 0;

  182. 		}

  183. 

  184. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  185. 			af = 1;

  186. 		}

  187. 	else {

  188. 			af = 0;

  189. 		}

  190. }

  191. 

  192. static void flag_add8 (uint8_t v1, uint8_t v2) {

  193. 	/* v1 = destination operand, v2 = source operand */

  194. 	uint16_t	dst;

  195. 

  196. 	dst = (uint16_t) v1 + (uint16_t) v2;

  197. 	flag_szp8 ( (uint8_t) dst);

  198. 	if (dst & 0xFF00) {

  199. 			cf = 1;

  200. 		}

  201. 	else {

  202. 			cf = 0;

  203. 		}

  204. 

  205. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x80) == 0x80) {

  206. 			of = 1;

  207. 		}

  208. 	else {

  209. 			of = 0;

  210. 		}

  211. 

  212. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  213. 			af = 1;

  214. 		}

  215. 	else {

  216. 			af = 0;

  217. 		}

  218. }

  219. 

  220. static void flag_add16 (uint16_t v1, uint16_t v2) {

  221. 	/* v1 = destination operand, v2 = source operand */

  222. 	uint32_t	dst;

  223. 

  224. 	dst = (uint32_t) v1 + (uint32_t) v2;

  225. 	flag_szp16 ( (uint16_t) dst);

  226. 	if (dst & 0xFFFF0000) {

  227. 			cf = 1;

  228. 		}

  229. 	else {

  230. 			cf = 0;

  231. 		}

  232. 

  233. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x8000) == 0x8000) {

  234. 			of = 1;

  235. 		}

  236. 	else {

  237. 			of = 0;

  238. 		}

  239. 

  240. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  241. 			af = 1;

  242. 		}

  243. 	else {

  244. 			af = 0;

  245. 		}

  246. }

  247. 

  248. static void flag_sbb8 (uint8_t v1, uint8_t v2, uint8_t v3) {

  249. 

  250. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  251. 	uint16_t	dst;

  252. 

  253. 	v2 += v3;

  254. 	dst = (uint16_t) v1 - (uint16_t) v2;

  255. 	flag_szp8 ( (uint8_t) dst);

  256. 	if (dst & 0xFF00) {

  257. 			cf = 1;

  258. 		}

  259. 	else {

  260. 			cf = 0;

  261. 		}

  262. 

  263. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x80) {

  264. 			of = 1;

  265. 		}

  266. 	else {

  267. 			of = 0;

  268. 		}

  269. 

  270. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  271. 			af = 1;

  272. 		}

  273. 	else {

  274. 			af = 0;

  275. 		}

  276. }

  277. 

  278. static void flag_sbb16 (uint16_t v1, uint16_t v2, uint16_t v3) {

  279. 

  280. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  281. 	uint32_t	dst;

  282. 

  283. 	v2 += v3;

  284. 	dst = (uint32_t) v1 - (uint32_t) v2;

  285. 	flag_szp16 ( (uint16_t) dst);

  286. 	if (dst & 0xFFFF0000) {

  287. 			cf = 1;

  288. 		}

  289. 	else {

  290. 			cf = 0;

  291. 		}

  292. 

  293. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x8000) {

  294. 			of = 1;

  295. 		}

  296. 	else {

  297. 			of = 0;

  298. 		}

  299. 

  300. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  301. 			af = 1;

  302. 		}

  303. 	else {

  304. 			af = 0;

  305. 		}

  306. }

  307. 

  308. static void flag_sub8 (uint8_t v1, uint8_t v2) {

  309. 

  310. 	/* v1 = destination operand, v2 = source operand */

  311. 	uint16_t	dst;

  312. 

  313. 	dst = (uint16_t) v1 - (uint16_t) v2;

  314. 	flag_szp8 ( (uint8_t) dst);

  315. 	if (dst & 0xFF00) {

  316. 			cf = 1;

  317. 		}

  318. 	else {

  319. 			cf = 0;

  320. 		}

  321. 

  322. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x80) {

  323. 			of = 1;

  324. 		}

  325. 	else {

  326. 			of = 0;

  327. 		}

  328. 

  329. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  330. 			af = 1;

  331. 		}

  332. 	else {

  333. 			af = 0;

  334. 		}

  335. }

  336. 

  337. static void flag_sub16 (uint16_t v1, uint16_t v2) {

  338. 

  339. 	/* v1 = destination operand, v2 = source operand */

  340. 	uint32_t	dst;

  341. 

  342. 	dst = (uint32_t) v1 - (uint32_t) v2;

  343. 	flag_szp16 ( (uint16_t) dst);

  344. 	if (dst & 0xFFFF0000) {

  345. 			cf = 1;

  346. 		}

  347. 	else {

  348. 			cf = 0;

  349. 		}

  350. 

  351. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x8000) {

  352. 			of = 1;

  353. 		}

  354. 	else {

  355. 			of = 0;

  356. 		}

  357. 

  358. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  359. 			af = 1;

  360. 		}

  361. 	else {

  362. 			af = 0;

  363. 		}

  364. }

  365. 

  366. static void op_adc8() {

  367. 	res8 = oper1b + oper2b + cf;

  368. 	flag_adc8 (oper1b, oper2b, cf);

  369. }

  370. 

  371. static void op_adc16() {

  372. 	res16 = oper1 + oper2 + cf;

  373. 	flag_adc16 (oper1, oper2, cf);

  374. }

  375. 

  376. static void op_add8() {

  377. 	res8 = oper1b + oper2b;

  378. 	flag_add8 (oper1b, oper2b);

  379. }

  380. 

  381. static void op_add16() {

  382. 	res16 = oper1 + oper2;

  383. 	flag_add16 (oper1, oper2);

  384. }

  385. 

  386. static void op_and8() {

  387. 	res8 = oper1b & oper2b;

  388. 	flag_log8 (res8);

  389. }

  390. 

  391. static void op_and16() {

  392. 	res16 = oper1 & oper2;

  393. 	flag_log16 (res16);

  394. }

  395. 

  396. static void op_or8() {

  397. 	res8 = oper1b | oper2b;

  398. 	flag_log8 (res8);

  399. }

  400. 

  401. static void op_or16() {

  402. 	res16 = oper1 | oper2;

  403. 	flag_log16 (res16);

  404. }

  405. 

  406. static void op_xor8() {

  407. 	res8 = oper1b ^ oper2b;

  408. 	flag_log8 (res8);

  409. }

  410. 

  411. static void op_xor16() {

  412. 	res16 = oper1 ^ oper2;

  413. 	flag_log16 (res16);

  414. }

  415. 

  416. static void op_sub8() {

  417. 	res8 = oper1b - oper2b;

  418. 	flag_sub8 (oper1b, oper2b);

  419. }

  420. 

  421. static void op_sub16() {

  422. 	res16 = oper1 - oper2;

  423. 	flag_sub16 (oper1, oper2);

  424. }

  425. 

  426. static void op_sbb8() {

  427. 	res8 = oper1b - (oper2b + cf);

  428. 	flag_sbb8 (oper1b, oper2b, cf);

  429. }

  430. 

  431. static void op_sbb16() {

  432. 	res16 = oper1 - (oper2 + cf);

  433. 	flag_sbb16 (oper1, oper2, cf);

  434. }

  435. 

  436. static void getea (uint8_t rmval) {

  437. 	uint32_t	tempea;

  438. 

  439. 	tempea = 0;

  440. 	switch (mode) {

  441. 			case 0:

  442. 				switch (rmval) {

  443. 						case 0:

  444. 							tempea = regs.wordregs[regbx] + regs.wordregs[regsi];

  445. 							break;

  446. 						case 1:

  447. 							tempea = regs.wordregs[regbx] + regs.wordregs[regdi];

  448. 							break;

  449. 						case 2:

  450. 							tempea = regs.wordregs[regbp] + regs.wordregs[regsi];

  451. 							break;

  452. 						case 3:

  453. 							tempea = regs.wordregs[regbp] + regs.wordregs[regdi];

  454. 							break;

  455. 						case 4:

  456. 							tempea = regs.wordregs[regsi];

  457. 							break;

  458. 						case 5:

  459. 							tempea = regs.wordregs[regdi];

  460. 							break;

  461. 						case 6:

  462. 							tempea = disp16;

  463. 							break;

  464. 						case 7:

  465. 							tempea = regs.wordregs[regbx];

  466. 							break;

  467. 					}

  468. 				break;

  469. 

  470. 			case 1:

  471. 			case 2:

  472. 				switch (rmval) {

  473. 						case 0:

  474. 							tempea = regs.wordregs[regbx] + regs.wordregs[regsi] + disp16;

  475. 							break;

  476. 						case 1:

  477. 							tempea = regs.wordregs[regbx] + regs.wordregs[regdi] + disp16;

  478. 							break;

  479. 						case 2:

  480. 							tempea = regs.wordregs[regbp] + regs.wordregs[regsi] + disp16;

  481. 							break;

  482. 						case 3:

  483. 							tempea = regs.wordregs[regbp] + regs.wordregs[regdi] + disp16;

  484. 							break;

  485. 						case 4:

  486. 							tempea = regs.wordregs[regsi] + disp16;

  487. 							break;

  488. 						case 5:

  489. 							tempea = regs.wordregs[regdi] + disp16;

  490. 							break;

  491. 						case 6:

  492. 							tempea = regs.wordregs[regbp] + disp16;

  493. 							break;

  494. 						case 7:

  495. 							tempea = regs.wordregs[regbx] + disp16;

  496. 							break;

  497. 					}

  498. 				break;

  499. 		}

  500. 

  501. 	ea = (tempea & 0xFFFF) + (useseg << 4);

  502. }

  503. 

  504. static void push (uint16_t pushval) {

  505. 	regs.wordregs[regsp] = regs.wordregs[regsp] - 2;

  506. 	putmem16 (segregs[regss], regs.wordregs[regsp], pushval);

  507. }

  508. 

  509. static uint16_t pop() {

  510. 

  511. 	uint16_t	tempval;

  512. 

  513. 	tempval = getmem16 (segregs[regss], regs.wordregs[regsp]);

  514. 	regs.wordregs[regsp] = regs.wordregs[regsp] + 2;

  515. 	return tempval;

  516. }

  517. 

  518. static uint16_t readrm16 (uint8_t rmval) {

  519. 	if (mode < 3) {

  520. 			getea (rmval);

  521. 			return read86 (ea) | ( (uint16_t) read86 (ea + 1) << 8);

  522. 		}

  523. 	else {

  524. 			return getreg16 (rmval);

  525. 		}

  526. }

  527. 

  528. static uint8_t readrm8 (uint8_t rmval) {

  529. 	if (mode < 3) {

  530. 			getea (rmval);

  531. 			return read86 (ea);

  532. 		}

  533. 	else {

  534. 			return getreg8 (rmval);

  535. 		}

  536. }

  537. 

  538. static void writerm16 (uint8_t rmval, uint16_t value) {

  539. 	if (mode < 3) {

  540. 			getea (rmval);

  541. 			write86 (ea, value & 0xFF);

  542. 			write86 (ea + 1, value >> 8);

  543. 		}

  544. 	else {

  545. 			putreg16 (rmval, value);

  546. 		}

  547. }

  548. 

  549. static void writerm8 (uint8_t rmval, uint8_t value) {

  550. 	if (mode < 3) {

  551. 			getea (rmval);

  552. 			write86 (ea, value);

  553. 		}

  554. 	else {

  555. 			putreg8 (rmval, value);

  556. 		}

  557. }

  558. 

  559. static uint8_t op_grp2_8 (uint8_t cnt) {

  560. 

  561. 	uint16_t	s;

  562. 	uint16_t	shift;

  563. 	uint16_t	oldcf;

  564. 	uint16_t	msb;

  565. 

  566. 	s = oper1b;

  567. 	oldcf = cf;

  568. 	cnt &= 0x1F;

  569. 	switch (reg) {

  570. 			case 0: /* ROL r/m8 */

  571. 				for (shift = 1; shift <= cnt; shift++) {

  572. 						if (s & 0x80) {

  573. 								cf = 1;

  574. 							}

  575. 						else {

  576. 								cf = 0;

  577. 							}

  578. 

  579. 						s = s << 1;

  580. 						s = s | cf;

  581. 					}

  582. 

  583. 				if (cnt == 1) {

  584. 						//of = cf ^ ( (s >> 7) & 1);

  585. 					if ((s & 0x80) && cf) of = 1; else of = 0;

  586. 					} else of = 0;

  587. 				break;

  588. 

  589. 			case 1: /* ROR r/m8 */

  590. 				for (shift = 1; shift <= cnt; shift++) {

  591. 						cf = s & 1;

  592. 						s = (s >> 1) | (cf << 7);

  593. 					}

  594. 

  595. 				if (cnt == 1) {

  596. 						of = (s >> 7) ^ ( (s >> 6) & 1);

  597. 					}

  598. 				break;

  599. 

  600. 			case 2: /* RCL r/m8 */

  601. 				for (shift = 1; shift <= cnt; shift++) {

  602. 						oldcf = cf;

  603. 						if (s & 0x80) {

  604. 								cf = 1;

  605. 							}

  606. 						else {

  607. 								cf = 0;

  608. 							}

  609. 

  610. 						s = s << 1;

  611. 						s = s | oldcf;

  612. 					}

  613. 

  614. 				if (cnt == 1) {

  615. 						of = cf ^ ( (s >> 7) & 1);

  616. 					}

  617. 				break;

  618. 

  619. 			case 3: /* RCR r/m8 */

  620. 				for (shift = 1; shift <= cnt; shift++) {

  621. 						oldcf = cf;

  622. 						cf = s & 1;

  623. 						s = (s >> 1) | (oldcf << 7);

  624. 					}

  625. 

  626. 				if (cnt == 1) {

  627. 						of = (s >> 7) ^ ( (s >> 6) & 1);

  628. 					}

  629. 				break;

  630. 

  631. 			case 4:

  632. 			case 6: /* SHL r/m8 */

  633. 				for (shift = 1; shift <= cnt; shift++) {

  634. 						if (s & 0x80) {

  635. 								cf = 1;

  636. 							}

  637. 						else {

  638. 								cf = 0;

  639. 							}

  640. 

  641. 						s = (s << 1) & 0xFF;

  642. 					}

  643. 

  644. 				if ( (cnt == 1) && (cf == (s >> 7) ) ) {

  645. 						of = 0;

  646. 					}

  647. 				else {

  648. 						of = 1;

  649. 					}

  650. 

  651. 				flag_szp8 ( (uint8_t) s);

  652. 				break;

  653. 

  654. 			case 5: /* SHR r/m8 */

  655. 				if ( (cnt == 1) && (s & 0x80) ) {

  656. 						of = 1;

  657. 					}

  658. 				else {

  659. 						of = 0;

  660. 					}

  661. 

  662. 				for (shift = 1; shift <= cnt; shift++) {

  663. 						cf = s & 1;

  664. 						s = s >> 1;

  665. 					}

  666. 

  667. 				flag_szp8 ( (uint8_t) s);

  668. 				break;

  669. 

  670. 			case 7: /* SAR r/m8 */

  671. 				for (shift = 1; shift <= cnt; shift++) {

  672. 						msb = s & 0x80;

  673. 						cf = s & 1;

  674. 						s = (s >> 1) | msb;

  675. 					}

  676. 

  677. 				of = 0;

  678. 				flag_szp8 ( (uint8_t) s);

  679. 				break;

  680. 		}

  681. 

  682. 	return s & 0xFF;

  683. }

  684. 

  685. static uint16_t op_grp2_16 (uint8_t cnt) {

  686. 

  687. 	uint32_t	s;

  688. 	uint32_t	shift;

  689. 	uint32_t	oldcf;

  690. 	uint32_t	msb;

  691. 

  692. 	s = oper1;

  693. 	oldcf = cf;

  694. 	cnt &= 0x1F;

  695. 	switch (reg) {

  696. 			case 0: /* ROL r/m8 */

  697. 				for (shift = 1; shift <= cnt; shift++) {

  698. 						if (s & 0x8000) {

  699. 								cf = 1;

  700. 							}

  701. 						else {

  702. 								cf = 0;

  703. 							}

  704. 

  705. 						s = s << 1;

  706. 						s = s | cf;

  707. 					}

  708. 

  709. 				if (cnt == 1) {

  710. 						of = cf ^ ( (s >> 15) & 1);

  711. 					}

  712. 				break;

  713. 

  714. 			case 1: /* ROR r/m8 */

  715. 				for (shift = 1; shift <= cnt; shift++) {

  716. 						cf = s & 1;

  717. 						s = (s >> 1) | (cf << 15);

  718. 					}

  719. 

  720. 				if (cnt == 1) {

  721. 						of = (s >> 15) ^ ( (s >> 14) & 1);

  722. 					}

  723. 				break;

  724. 

  725. 			case 2: /* RCL r/m8 */

  726. 				for (shift = 1; shift <= cnt; shift++) {

  727. 						oldcf = cf;

  728. 						if (s & 0x8000) {

  729. 								cf = 1;

  730. 							}

  731. 						else {

  732. 								cf = 0;

  733. 							}

  734. 

  735. 						s = s << 1;

  736. 						s = s | oldcf;

  737. 					}

  738. 

  739. 				if (cnt == 1) {

  740. 						of = cf ^ ( (s >> 15) & 1);

  741. 					}

  742. 				break;

  743. 

  744. 			case 3: /* RCR r/m8 */

  745. 				for (shift = 1; shift <= cnt; shift++) {

  746. 						oldcf = cf;

  747. 						cf = s & 1;

  748. 						s = (s >> 1) | (oldcf << 15);

  749. 					}

  750. 

  751. 				if (cnt == 1) {

  752. 						of = (s >> 15) ^ ( (s >> 14) & 1);

  753. 					}

  754. 				break;

  755. 

  756. 			case 4:

  757. 			case 6: /* SHL r/m8 */

  758. 				for (shift = 1; shift <= cnt; shift++) {

  759. 						if (s & 0x8000) {

  760. 								cf = 1;

  761. 							}

  762. 						else {

  763. 								cf = 0;

  764. 							}

  765. 

  766. 						s = (s << 1) & 0xFFFF;

  767. 					}

  768. 

  769. 				if ( (cnt == 1) && (cf == (s >> 15) ) ) {

  770. 						of = 0;

  771. 					}

  772. 				else {

  773. 						of = 1;

  774. 					}

  775. 

  776. 				flag_szp16 ( (uint16_t) s);

  777. 				break;

  778. 

  779. 			case 5: /* SHR r/m8 */

  780. 				if ( (cnt == 1) && (s & 0x8000) ) {

  781. 						of = 1;

  782. 					}

  783. 				else {

  784. 						of = 0;

  785. 					}

  786. 

  787. 				for (shift = 1; shift <= cnt; shift++) {

  788. 						cf = s & 1;

  789. 						s = s >> 1;

  790. 					}

  791. 

  792. 				flag_szp16 ( (uint16_t) s);

  793. 				break;

  794. 

  795. 			case 7: /* SAR r/m8 */

  796. 				for (shift = 1; shift <= cnt; shift++) {

  797. 						msb = s & 0x8000;

  798. 						cf = s & 1;

  799. 						s = (s >> 1) | msb;

  800. 					}

  801. 

  802. 				of = 0;

  803. 				flag_szp16 ( (uint16_t) s);

  804. 				break;

  805. 		}

  806. 

  807. 	return (uint16_t) s & 0xFFFF;

  808. }

  809. 

  810. static void op_div8 (uint16_t valdiv, uint8_t divisor) {

  811. 	if (divisor == 0) {

  812. 			intcall86 (0);

  813. 			return;

  814. 		}

  815. 

  816. 	if ( (valdiv / (uint16_t) divisor) > 0xFF) {

  817. 			intcall86 (0);

  818. 			return;

  819. 		}

  820. 

  821. 	regs.byteregs[regah] = valdiv % (uint16_t) divisor;

  822. 	regs.byteregs[regal] = valdiv / (uint16_t) divisor;

  823. }

  824. 

  825. static void op_idiv8 (uint16_t valdiv, uint8_t divisor) {

  826. 

  827. 	uint16_t	s1;

  828. 	uint16_t	s2;

  829. 	uint16_t	d1;

  830. 	uint16_t	d2;

  831. 	int	sign;

  832. 

  833. 	if (divisor == 0) {

  834. 			intcall86 (0);

  835. 			return;

  836. 		}

  837. 

  838. 	s1 = valdiv;

  839. 	s2 = divisor;

  840. 	sign = ( ( (s1 ^ s2) & 0x8000) != 0);

  841. 	s1 = (s1 < 0x8000) ? s1 : ( (~s1 + 1) & 0xffff);

  842. 	s2 = (s2 < 0x8000) ? s2 : ( (~s2 + 1) & 0xffff);

  843. 	d1 = s1 / s2;

  844. 	d2 = s1 % s2;

  845. 	if (d1 & 0xFF00) {

  846. 			intcall86 (0);

  847. 			return;

  848. 		}

  849. 

  850. 	if (sign) {

  851. 			d1 = (~d1 + 1) & 0xff;

  852. 			d2 = (~d2 + 1) & 0xff;

  853. 		}

  854. 

  855. 	regs.byteregs[regah] = (uint8_t) d2;

  856. 	regs.byteregs[regal] = (uint8_t) d1;

  857. }

  858. 

  859. static void op_grp3_8() {

  860. 	oper1 = signext (oper1b);

  861. 	oper2 = signext (oper2b);

  862. 	switch (reg) {

  863. 			case 0:

  864. 			case 1: /* TEST */

  865. 				flag_log8 (oper1b & getmem8 (segregs[regcs], ip) );

  866. 				StepIP (1);

  867. 				break;

  868. 

  869. 			case 2: /* NOT */

  870. 				res8 = ~oper1b;

  871. 				break;

  872. 

  873. 			case 3: /* NEG */

  874. 				res8 = (~oper1b) + 1;

  875. 				flag_sub8 (0, oper1b);

  876. 				if (res8 == 0) {

  877. 						cf = 0;

  878. 					}

  879. 				else {

  880. 						cf = 1;

  881. 					}

  882. 				break;

  883. 

  884. 			case 4: /* MUL */

  885. 				temp1 = (uint32_t) oper1b * (uint32_t) regs.byteregs[regal];

  886. 				regs.wordregs[regax] = temp1 & 0xFFFF;

  887. 				flag_szp8 ( (uint8_t) temp1);

  888. 				if (regs.byteregs[regah]) {

  889. 						cf = 1;

  890. 						of = 1;

  891. 					}

  892. 				else {

  893. 						cf = 0;

  894. 						of = 0;

  895. 					}

  896. 				break;

  897. 

  898. 			case 5: /* IMUL */

  899. 				oper1 = signext (oper1b);

  900. 				temp1 = signext (regs.byteregs[regal]);

  901. 				temp2 = oper1;

  902. 				if ( (temp1 & 0x80) == 0x80) {

  903. 						temp1 = temp1 | 0xFFFFFF00;

  904. 					}

  905. 

  906. 				if ( (temp2 & 0x80) == 0x80) {

  907. 						temp2 = temp2 | 0xFFFFFF00;

  908. 					}

  909. 

  910. 				temp3 = (temp1 * temp2) & 0xFFFF;

  911. 				regs.wordregs[regax] = temp3 & 0xFFFF;

  912. 				if (regs.byteregs[regah]) {

  913. 						cf = 1;

  914. 						of = 1;

  915. 					}

  916. 				else {

  917. 						cf = 0;

  918. 						of = 0;

  919. 					}

  920. 				break;

  921. 

  922. 			case 6: /* DIV */

  923. 				op_div8 (regs.wordregs[regax], oper1b);

  924. 				break;

  925. 

  926. 			case 7: /* IDIV */

  927. 				op_idiv8 (regs.wordregs[regax], oper1b);

  928. 				break;

  929. 		}

  930. }

  931. 

  932. static void op_div16 (uint32_t valdiv, uint16_t divisor) {

  933. 	if (divisor == 0) {

  934. 			intcall86 (0);

  935. 			return;

  936. 		}

  937. 

  938. 	if ( (valdiv / (uint32_t) divisor) > 0xFFFF) {

  939. 			intcall86 (0);

  940. 			return;

  941. 		}

  942. 

  943. 	regs.wordregs[regdx] = valdiv % (uint32_t) divisor;

  944. 	regs.wordregs[regax] = valdiv / (uint32_t) divisor;

  945. }

  946. 

  947. static void op_idiv16 (uint32_t valdiv, uint16_t divisor) {

  948. 

  949. 	uint32_t	d1;

  950. 	uint32_t	d2;

  951. 	uint32_t	s1;

  952. 	uint32_t	s2;

  953. 	int	sign;

  954. 

  955. 	if (divisor == 0) {

  956. 			intcall86 (0);

  957. 			return;

  958. 		}

  959. 

  960. 	s1 = valdiv;

  961. 	s2 = divisor;

  962. 	s2 = (s2 & 0x8000) ? (s2 | 0xffff0000) : s2;

  963. 	sign = ( ( (s1 ^ s2) & 0x80000000) != 0);

  964. 	s1 = (s1 < 0x80000000) ? s1 : ( (~s1 + 1) & 0xffffffff);

  965. 	s2 = (s2 < 0x80000000) ? s2 : ( (~s2 + 1) & 0xffffffff);

  966. 	d1 = s1 / s2;

  967. 	d2 = s1 % s2;

  968. 	if (d1 & 0xFFFF0000) {

  969. 			intcall86 (0);

  970. 			return;

  971. 		}

  972. 

  973. 	if (sign) {

  974. 			d1 = (~d1 + 1) & 0xffff;

  975. 			d2 = (~d2 + 1) & 0xffff;

  976. 		}

  977. 

  978. 	regs.wordregs[regax] = d1;

  979. 	regs.wordregs[regdx] = d2;

  980. }

  981. 

  982. static void op_grp3_16() {

  983. 	switch (reg) {

  984. 			case 0:

  985. 			case 1: /* TEST */

  986. 				flag_log16 (oper1 & getmem16 (segregs[regcs], ip) );

  987. 				StepIP (2);

  988. 				break;

  989. 

  990. 			case 2: /* NOT */

  991. 				res16 = ~oper1;

  992. 				break;

  993. 

  994. 			case 3: /* NEG */

  995. 				res16 = (~oper1) + 1;

  996. 				flag_sub16 (0, oper1);

  997. 				if (res16) {

  998. 						cf = 1;

  999. 					}

  1000. 				else {

  1001. 						cf = 0;

  1002. 					}

  1003. 				break;

  1004. 

  1005. 			case 4: /* MUL */

  1006. 				temp1 = (uint32_t) oper1 * (uint32_t) regs.wordregs[regax];

  1007. 				regs.wordregs[regax] = temp1 & 0xFFFF;

  1008. 				regs.wordregs[regdx] = temp1 >> 16;

  1009. 				flag_szp16 ( (uint16_t) temp1);

  1010. 				if (regs.wordregs[regdx]) {

  1011. 						cf = 1;

  1012. 						of = 1;

  1013. 					}

  1014. 				else {

  1015. 						cf = 0;

  1016. 						of = 0;

  1017. 					}

  1018. 				break;

  1019. 

  1020. 			case 5: /* IMUL */

  1021. 				temp1 = regs.wordregs[regax];

  1022. 				temp2 = oper1;

  1023. 				if (temp1 & 0x8000) {

  1024. 						temp1 |= 0xFFFF0000;

  1025. 					}

  1026. 

  1027. 				if (temp2 & 0x8000) {

  1028. 						temp2 |= 0xFFFF0000;

  1029. 					}

  1030. 

  1031. 				temp3 = temp1 * temp2;

  1032. 				regs.wordregs[regax] = temp3 & 0xFFFF;	/* into register ax */

  1033. 				regs.wordregs[regdx] = temp3 >> 16;	/* into register dx */

  1034. 				if (regs.wordregs[regdx]) {

  1035. 						cf = 1;

  1036. 						of = 1;

  1037. 					}

  1038. 				else {

  1039. 						cf = 0;

  1040. 						of = 0;

  1041. 					}

  1042. 				break;

  1043. 

  1044. 			case 6: /* DIV */

  1045. 				op_div16 ( ( (uint32_t) regs.wordregs[regdx] << 16) + regs.wordregs[regax], oper1);

  1046. 				break;

  1047. 

  1048. 			case 7: /* DIV */

  1049. 				op_idiv16 ( ( (uint32_t) regs.wordregs[regdx] << 16) + regs.wordregs[regax], oper1);

  1050. 				break;

  1051. 		}

  1052. }

  1053. 

  1054. static void op_grp5() {

  1055. 	switch (reg) {

  1056. 			case 0: /* INC Ev */

  1057. 				oper2 = 1;

  1058. 				tempcf = cf;

  1059. 				op_add16();

  1060. 				cf = tempcf;

  1061. 				writerm16 (rm, res16);

  1062. 				break;

  1063. 

  1064. 			case 1: /* DEC Ev */

  1065. 				oper2 = 1;

  1066. 				tempcf = cf;

  1067. 				op_sub16();

  1068. 				cf = tempcf;

  1069. 				writerm16 (rm, res16);

  1070. 				break;

  1071. 

  1072. 			case 2: /* CALL Ev */

  1073. 				push (ip);

  1074. 				ip = oper1;

  1075. 				break;

  1076. 

  1077. 			case 3: /* CALL Mp */

  1078. 				push (segregs[regcs]);

  1079. 				push (ip);

  1080. 				getea (rm);

  1081. 				ip = (uint16_t) read86 (ea) + (uint16_t) read86 (ea + 1) * 256;

  1082. 				segregs[regcs] = (uint16_t) read86 (ea + 2) + (uint16_t) read86 (ea + 3) * 256;

  1083. 				break;

  1084. 

  1085. 			case 4: /* JMP Ev */

  1086. 				ip = oper1;

  1087. 				break;

  1088. 

  1089. 			case 5: /* JMP Mp */

  1090. 				getea (rm);

  1091. 				ip = (uint16_t) read86 (ea) + (uint16_t) read86 (ea + 1) * 256;

  1092. 				segregs[regcs] = (uint16_t) read86 (ea + 2) + (uint16_t) read86 (ea + 3) * 256;

  1093. 				break;

  1094. 

  1095. 			case 6: /* PUSH Ev */

  1096. 				push (oper1);

  1097. 				break;

  1098. 		}

  1099. }

  1100. 

  1101. void intcall86(uint8_t intnum) {

  1102.     if (intnum == 0) {

  1103.         fprintf(stderr, "INT 0 called, halting\n");

  1104.         hltstate = 1;

  1105.         return;

  1106.     }

  1107.     if (INTHOOKS[intnum] != NULL) {

  1108.         INTHOOKS[intnum]();

  1109.         return;

  1110.     }

  1111.     fprintf(stderr, "Unknown INT called: %x\n", intnum);

  1112. }

  1113. 

  1114. uint16_t makeflagsword() {

  1115. 	return 2 | (uint16_t) cf | ((uint16_t) pf << 2) | ((uint16_t) af << 4) | \

  1116.         ((uint16_t) zf << 6) | ((uint16_t) sf << 7) | ((uint16_t) tf << 8) | \

  1117.         ((uint16_t) ifl << 9) | ((uint16_t) df << 10) | ((uint16_t) of << 11);

  1118. }

  1119. 

  1120. void decodeflagsword(uint16_t x) {

  1121. 	cf = x & 1;

  1122. 	pf = (x >> 2) & 1;

  1123. 	af = (x >> 4) & 1;

  1124. 	zf = (x >> 6) & 1;

  1125. 	sf = (x >> 7) & 1;

  1126. 	tf = (x >> 8) & 1;

  1127. 	ifl = (x >> 9) & 1;

  1128. 	df = (x >> 10) & 1;

  1129. 	of = (x >> 11) & 1;

  1130. }

  1131. 

  1132. static void modregrm() {

  1133. 	addrbyte = getmem8(segregs[regcs], ip);

  1134. 	StepIP(1);

  1135. 	mode = addrbyte >> 6;

  1136. 	reg = (addrbyte >> 3) & 7;

  1137. 	rm = addrbyte & 7;

  1138. 	switch(mode)

  1139. 	{

  1140.         case 0:

  1141.         if (rm == 6) {

  1142.             disp16 = getmem16(segregs[regcs], ip);

  1143.             StepIP(2);

  1144.         }

  1145.         if (((rm == 2) || (rm == 3)) && !segoverride) {

  1146.             useseg = segregs[regss];

  1147.         }

  1148.         break;

  1149. 

  1150.         case 1:

  1151.         disp16 = signext(getmem8(segregs[regcs], ip));

  1152.         StepIP(1);

  1153.         if (((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) {

  1154.             useseg = segregs[regss];

  1155.         }

  1156.         break;

  1157. 

  1158.         case 2:

  1159.         disp16 = getmem16(segregs[regcs], ip);

  1160.         StepIP(2);

  1161.         if (((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) {

  1162.             useseg = segregs[regss];

  1163.         }

  1164.         break;

  1165. 

  1166.         default:

  1167.         disp8 = 0;

  1168.         disp16 = 0;

  1169. 	}

  1170. }

  1171. 

  1172. int exec86(int execloops) {

  1173. 	int loopcount;

  1174. 	uint8_t docontinue;

  1175. 	static uint16_t firstip;

  1176. 	uint16_t oldcf;

  1177. 

  1178. 	for (loopcount = 0; loopcount < execloops; loopcount++) {

  1179.         if (hltstate) return 0;

  1180. 

  1181.         reptype = 0;

  1182.         segoverride = 0;

  1183.         useseg = segregs[regds];

  1184.         docontinue = 0;

  1185.         firstip = ip;

  1186. 

  1187.         while (!docontinue) {

  1188.             segregs[regcs] = segregs[regcs] & 0xFFFF;

  1189.             ip = ip & 0xFFFF;

  1190.             opcode = getmem8 (segregs[regcs], ip);

  1191.             StepIP (1);

  1192. 

  1193.             switch (opcode) {

  1194.                         /* segment prefix check */

  1195.                     case 0x2E:	/* segment segregs[regcs] */

  1196.                         useseg = segregs[regcs];

  1197.                         segoverride = 1;

  1198.                         break;

  1199. 

  1200.                     case 0x3E:	/* segment segregs[regds] */

  1201.                         useseg = segregs[regds];

  1202.                         segoverride = 1;

  1203.                         break;

  1204. 

  1205.                     case 0x26:	/* segment segregs[reges] */

  1206.                         useseg = segregs[reges];

  1207.                         segoverride = 1;

  1208.                         break;

  1209. 

  1210.                     case 0x36:	/* segment segregs[regss] */

  1211.                         useseg = segregs[regss];

  1212.                         segoverride = 1;

  1213.                         break;

  1214. 

  1215.                         /* repetition prefix check */

  1216.                     case 0xF3:	/* REP/REPE/REPZ */

  1217.                         reptype = 1;

  1218.                         break;

  1219. 

  1220.                     case 0xF2:	/* REPNE/REPNZ */

  1221.                         reptype = 2;

  1222.                         break;

  1223. 

  1224.                     default:

  1225.                         docontinue = 1;

  1226.                         break;

  1227.                 }

  1228.         }

  1229. 

  1230.         switch (opcode) {

  1231.             case 0x0:	/* 00 ADD Eb Gb */

  1232.                 modregrm();

  1233.                 oper1b = readrm8 (rm);

  1234.                 oper2b = getreg8 (reg);

  1235.                 op_add8();

  1236.                 writerm8 (rm, res8);

  1237.                 break;

  1238. 

  1239.             case 0x1:	/* 01 ADD Ev Gv */

  1240.                 modregrm();

  1241.                 oper1 = readrm16 (rm);

  1242.                 oper2 = getreg16 (reg);

  1243.                 op_add16();

  1244.                 writerm16 (rm, res16);

  1245.                 break;

  1246. 

  1247.             case 0x2:	/* 02 ADD Gb Eb */

  1248.                 modregrm();

  1249.                 oper1b = getreg8 (reg);

  1250.                 oper2b = readrm8 (rm);

  1251.                 op_add8();

  1252.                 putreg8 (reg, res8);

  1253.                 break;

  1254. 

  1255.             case 0x3:	/* 03 ADD Gv Ev */

  1256.                 modregrm();

  1257.                 oper1 = getreg16 (reg);

  1258.                 oper2 = readrm16 (rm);

  1259.                 op_add16();

  1260.                 putreg16 (reg, res16);

  1261.                 break;

  1262. 

  1263.             case 0x4:	/* 04 ADD regs.byteregs[regal] Ib */

  1264.                 oper1b = regs.byteregs[regal];

  1265.                 oper2b = getmem8 (segregs[regcs], ip);

  1266.                 StepIP (1);

  1267.                 op_add8();

  1268.                 regs.byteregs[regal] = res8;

  1269.                 break;

  1270. 

  1271.             case 0x5:	/* 05 ADD eAX Iv */

  1272.                 oper1 = regs.wordregs[regax];

  1273.                 oper2 = getmem16 (segregs[regcs], ip);

  1274.                 StepIP (2);

  1275.                 op_add16();

  1276.                 regs.wordregs[regax] = res16;

  1277.                 break;

  1278. 

  1279.             case 0x6:	/* 06 PUSH segregs[reges] */

  1280.                 push (segregs[reges]);

  1281.                 break;

  1282. 

  1283.             case 0x7:	/* 07 POP segregs[reges] */

  1284.                 segregs[reges] = pop();

  1285.                 break;

  1286. 

  1287.             case 0x8:	/* 08 OR Eb Gb */

  1288.                 modregrm();

  1289.                 oper1b = readrm8 (rm);

  1290.                 oper2b = getreg8 (reg);

  1291.                 op_or8();

  1292.                 writerm8 (rm, res8);

  1293.                 break;

  1294. 

  1295.             case 0x9:	/* 09 OR Ev Gv */

  1296.                 modregrm();

  1297.                 oper1 = readrm16 (rm);

  1298.                 oper2 = getreg16 (reg);

  1299.                 op_or16();

  1300.                 writerm16 (rm, res16);

  1301.                 break;

  1302. 

  1303.             case 0xA:	/* 0A OR Gb Eb */

  1304.                 modregrm();

  1305.                 oper1b = getreg8 (reg);

  1306.                 oper2b = readrm8 (rm);

  1307.                 op_or8();

  1308.                 putreg8 (reg, res8);

  1309.                 break;

  1310. 

  1311.             case 0xB:	/* 0B OR Gv Ev */

  1312.                 modregrm();

  1313.                 oper1 = getreg16 (reg);

  1314.                 oper2 = readrm16 (rm);

  1315.                 op_or16();

  1316.                 putreg16 (reg, res16);

  1317.                 break;

  1318. 

  1319.             case 0xC:	/* 0C OR regs.byteregs[regal] Ib */

  1320.                 oper1b = regs.byteregs[regal];

  1321.                 oper2b = getmem8 (segregs[regcs], ip);

  1322.                 StepIP (1);

  1323.                 op_or8();

  1324.                 regs.byteregs[regal] = res8;

  1325.                 break;

  1326. 

  1327.             case 0xD:	/* 0D OR eAX Iv */

  1328.                 oper1 = regs.wordregs[regax];

  1329.                 oper2 = getmem16 (segregs[regcs], ip);

  1330.                 StepIP (2);

  1331.                 op_or16();

  1332.                 regs.wordregs[regax] = res16;

  1333.                 break;

  1334. 

  1335.             case 0xE:	/* 0E PUSH segregs[regcs] */

  1336.                 push (segregs[regcs]);

  1337.                 break;

  1338. 

  1339.             case 0x10:	/* 10 ADC Eb Gb */

  1340.                 modregrm();

  1341.                 oper1b = readrm8 (rm);

  1342.                 oper2b = getreg8 (reg);

  1343.                 op_adc8();

  1344.                 writerm8 (rm, res8);

  1345.                 break;

  1346. 

  1347.             case 0x11:	/* 11 ADC Ev Gv */

  1348.                 modregrm();

  1349.                 oper1 = readrm16 (rm);

  1350.                 oper2 = getreg16 (reg);

  1351.                 op_adc16();

  1352.                 writerm16 (rm, res16);

  1353.                 break;

  1354. 

  1355.             case 0x12:	/* 12 ADC Gb Eb */

  1356.                 modregrm();

  1357.                 oper1b = getreg8 (reg);

  1358.                 oper2b = readrm8 (rm);

  1359.                 op_adc8();

  1360.                 putreg8 (reg, res8);

  1361.                 break;

  1362. 

  1363.             case 0x13:	/* 13 ADC Gv Ev */

  1364.                 modregrm();

  1365.                 oper1 = getreg16 (reg);

  1366.                 oper2 = readrm16 (rm);

  1367.                 op_adc16();

  1368.                 putreg16 (reg, res16);

  1369.                 break;

  1370. 

  1371.             case 0x14:	/* 14 ADC regs.byteregs[regal] Ib */

  1372.                 oper1b = regs.byteregs[regal];

  1373.                 oper2b = getmem8 (segregs[regcs], ip);

  1374.                 StepIP (1);

  1375.                 op_adc8();

  1376.                 regs.byteregs[regal] = res8;

  1377.                 break;

  1378. 

  1379.             case 0x15:	/* 15 ADC eAX Iv */

  1380.                 oper1 = regs.wordregs[regax];

  1381.                 oper2 = getmem16 (segregs[regcs], ip);

  1382.                 StepIP (2);

  1383.                 op_adc16();

  1384.                 regs.wordregs[regax] = res16;

  1385.                 break;

  1386. 

  1387.             case 0x16:	/* 16 PUSH segregs[regss] */

  1388.                 push (segregs[regss]);

  1389.                 break;

  1390. 

  1391.             case 0x17:	/* 17 POP segregs[regss] */

  1392.                 segregs[regss] = pop();

  1393.                 break;

  1394. 

  1395.             case 0x18:	/* 18 SBB Eb Gb */

  1396.                 modregrm();

  1397.                 oper1b = readrm8 (rm);

  1398.                 oper2b = getreg8 (reg);

  1399.                 op_sbb8();

  1400.                 writerm8 (rm, res8);

  1401.                 break;

  1402. 

  1403.             case 0x19:	/* 19 SBB Ev Gv */

  1404.                 modregrm();

  1405.                 oper1 = readrm16 (rm);

  1406.                 oper2 = getreg16 (reg);

  1407.                 op_sbb16();

  1408.                 writerm16 (rm, res16);

  1409.                 break;

  1410. 

  1411.             case 0x1A:	/* 1A SBB Gb Eb */

  1412.                 modregrm();

  1413.                 oper1b = getreg8 (reg);

  1414.                 oper2b = readrm8 (rm);

  1415.                 op_sbb8();

  1416.                 putreg8 (reg, res8);

  1417.                 break;

  1418. 

  1419.             case 0x1B:	/* 1B SBB Gv Ev */

  1420.                 modregrm();

  1421.                 oper1 = getreg16 (reg);

  1422.                 oper2 = readrm16 (rm);

  1423.                 op_sbb16();

  1424.                 putreg16 (reg, res16);

  1425.                 break;

  1426. 

  1427.             case 0x1C:	/* 1C SBB regs.byteregs[regal] Ib */

  1428.                 oper1b = regs.byteregs[regal];

  1429.                 oper2b = getmem8 (segregs[regcs], ip);

  1430.                 StepIP (1);

  1431.                 op_sbb8();

  1432.                 regs.byteregs[regal] = res8;

  1433.                 break;

  1434. 

  1435.             case 0x1D:	/* 1D SBB eAX Iv */

  1436.                 oper1 = regs.wordregs[regax];

  1437.                 oper2 = getmem16 (segregs[regcs], ip);

  1438.                 StepIP (2);

  1439.                 op_sbb16();

  1440.                 regs.wordregs[regax] = res16;

  1441.                 break;

  1442. 

  1443.             case 0x1E:	/* 1E PUSH segregs[regds] */

  1444.                 push (segregs[regds]);

  1445.                 break;

  1446. 

  1447.             case 0x1F:	/* 1F POP segregs[regds] */

  1448.                 segregs[regds] = pop();

  1449.                 break;

  1450. 

  1451.             case 0x20:	/* 20 AND Eb Gb */

  1452.                 modregrm();

  1453.                 oper1b = readrm8 (rm);

  1454.                 oper2b = getreg8 (reg);

  1455.                 op_and8();

  1456.                 writerm8 (rm, res8);

  1457.                 break;

  1458. 

  1459.             case 0x21:	/* 21 AND Ev Gv */

  1460.                 modregrm();

  1461.                 oper1 = readrm16 (rm);

  1462.                 oper2 = getreg16 (reg);

  1463.                 op_and16();

  1464.                 writerm16 (rm, res16);

  1465.                 break;

  1466. 

  1467.             case 0x22:	/* 22 AND Gb Eb */

  1468.                 modregrm();

  1469.                 oper1b = getreg8 (reg);

  1470.                 oper2b = readrm8 (rm);

  1471.                 op_and8();

  1472.                 putreg8 (reg, res8);

  1473.                 break;

  1474. 

  1475.             case 0x23:	/* 23 AND Gv Ev */

  1476.                 modregrm();

  1477.                 oper1 = getreg16 (reg);

  1478.                 oper2 = readrm16 (rm);

  1479.                 op_and16();

  1480.                 putreg16 (reg, res16);

  1481.                 break;

  1482. 

  1483.             case 0x24:	/* 24 AND regs.byteregs[regal] Ib */

  1484.                 oper1b = regs.byteregs[regal];

  1485.                 oper2b = getmem8 (segregs[regcs], ip);

  1486.                 StepIP (1);

  1487.                 op_and8();

  1488.                 regs.byteregs[regal] = res8;

  1489.                 break;

  1490. 

  1491.             case 0x25:	/* 25 AND eAX Iv */

  1492.                 oper1 = regs.wordregs[regax];

  1493.                 oper2 = getmem16 (segregs[regcs], ip);

  1494.                 StepIP (2);

  1495.                 op_and16();

  1496.                 regs.wordregs[regax] = res16;

  1497.                 break;

  1498. 

  1499.             case 0x27:	/* 27 DAA */

  1500.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1501.                         oper1 = regs.byteregs[regal] + 6;

  1502.                         regs.byteregs[regal] = oper1 & 255;

  1503.                         if (oper1 & 0xFF00) {

  1504.                                 cf = 1;

  1505.                             }

  1506.                         else {

  1507.                                 cf = 0;

  1508.                             }

  1509. 

  1510.                         af = 1;

  1511.                     }

  1512.                 else {

  1513.                         //af = 0;

  1514.                     }

  1515. 

  1516.                 if ( (regs.byteregs[regal]  > 0x9F) || (cf == 1) ) {

  1517.                         regs.byteregs[regal] = regs.byteregs[regal] + 0x60;

  1518.                         cf = 1;

  1519.                     }

  1520.                 else {

  1521.                         //cf = 0;

  1522.                     }

  1523. 

  1524.                 regs.byteregs[regal] = regs.byteregs[regal] & 255;

  1525.                 flag_szp8 (regs.byteregs[regal]);

  1526.                 break;

  1527. 

  1528.             case 0x28:	/* 28 SUB Eb Gb */

  1529.                 modregrm();

  1530.                 oper1b = readrm8 (rm);

  1531.                 oper2b = getreg8 (reg);

  1532.                 op_sub8();

  1533.                 writerm8 (rm, res8);

  1534.                 break;

  1535. 

  1536.             case 0x29:	/* 29 SUB Ev Gv */

  1537.                 modregrm();

  1538.                 oper1 = readrm16 (rm);

  1539.                 oper2 = getreg16 (reg);

  1540.                 op_sub16();

  1541.                 writerm16 (rm, res16);

  1542.                 break;

  1543. 

  1544.             case 0x2A:	/* 2A SUB Gb Eb */

  1545.                 modregrm();

  1546.                 oper1b = getreg8 (reg);

  1547.                 oper2b = readrm8 (rm);

  1548.                 op_sub8();

  1549.                 putreg8 (reg, res8);

  1550.                 break;

  1551. 

  1552.             case 0x2B:	/* 2B SUB Gv Ev */

  1553.                 modregrm();

  1554.                 oper1 = getreg16 (reg);

  1555.                 oper2 = readrm16 (rm);

  1556.                 op_sub16();

  1557.                 putreg16 (reg, res16);

  1558.                 break;

  1559. 

  1560.             case 0x2C:	/* 2C SUB regs.byteregs[regal] Ib */

  1561.                 oper1b = regs.byteregs[regal];

  1562.                 oper2b = getmem8 (segregs[regcs], ip);

  1563.                 StepIP (1);

  1564.                 op_sub8();

  1565.                 regs.byteregs[regal] = res8;

  1566.                 break;

  1567. 

  1568.             case 0x2D:	/* 2D SUB eAX Iv */

  1569.                 oper1 = regs.wordregs[regax];

  1570.                 oper2 = getmem16 (segregs[regcs], ip);

  1571.                 StepIP (2);

  1572.                 op_sub16();

  1573.                 regs.wordregs[regax] = res16;

  1574.                 break;

  1575. 

  1576.             case 0x2F:	/* 2F DAS */

  1577.                 if ( ( (regs.byteregs[regal] & 15) > 9) || (af == 1) ) {

  1578.                         oper1 = regs.byteregs[regal] - 6;

  1579.                         regs.byteregs[regal] = oper1 & 255;

  1580.                         if (oper1 & 0xFF00) {

  1581.                                 cf = 1;

  1582.                             }

  1583.                         else {

  1584.                                 cf = 0;

  1585.                             }

  1586. 

  1587.                         af = 1;

  1588.                     }

  1589.                 else {

  1590.                         af = 0;

  1591.                     }

  1592. 

  1593.                 if ( ( (regs.byteregs[regal] & 0xF0) > 0x90) || (cf == 1) ) {

  1594.                         regs.byteregs[regal] = regs.byteregs[regal] - 0x60;

  1595.                         cf = 1;

  1596.                     }

  1597.                 else {

  1598.                         cf = 0;

  1599.                     }

  1600. 

  1601.                 flag_szp8 (regs.byteregs[regal]);

  1602.                 break;

  1603. 

  1604.             case 0x30:	/* 30 XOR Eb Gb */

  1605.                 modregrm();

  1606.                 oper1b = readrm8 (rm);

  1607.                 oper2b = getreg8 (reg);

  1608.                 op_xor8();

  1609.                 writerm8 (rm, res8);

  1610.                 break;

  1611. 

  1612.             case 0x31:	/* 31 XOR Ev Gv */

  1613.                 modregrm();

  1614.                 oper1 = readrm16 (rm);

  1615.                 oper2 = getreg16 (reg);

  1616.                 op_xor16();

  1617.                 writerm16 (rm, res16);

  1618.                 break;

  1619. 

  1620.             case 0x32:	/* 32 XOR Gb Eb */

  1621.                 modregrm();

  1622.                 oper1b = getreg8 (reg);

  1623.                 oper2b = readrm8 (rm);

  1624.                 op_xor8();

  1625.                 putreg8 (reg, res8);

  1626.                 break;

  1627. 

  1628.             case 0x33:	/* 33 XOR Gv Ev */

  1629.                 modregrm();

  1630.                 oper1 = getreg16 (reg);

  1631.                 oper2 = readrm16 (rm);

  1632.                 op_xor16();

  1633.                 putreg16 (reg, res16);

  1634.                 break;

  1635. 

  1636.             case 0x34:	/* 34 XOR regs.byteregs[regal] Ib */

  1637.                 oper1b = regs.byteregs[regal];

  1638.                 oper2b = getmem8 (segregs[regcs], ip);

  1639.                 StepIP (1);

  1640.                 op_xor8();

  1641.                 regs.byteregs[regal] = res8;

  1642.                 break;

  1643. 

  1644.             case 0x35:	/* 35 XOR eAX Iv */

  1645.                 oper1 = regs.wordregs[regax];

  1646.                 oper2 = getmem16 (segregs[regcs], ip);

  1647.                 StepIP (2);

  1648.                 op_xor16();

  1649.                 regs.wordregs[regax] = res16;

  1650.                 break;

  1651. 

  1652.             case 0x37:	/* 37 AAA ASCII */

  1653.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1654.                         regs.byteregs[regal] = regs.byteregs[regal] + 6;

  1655.                         regs.byteregs[regah] = regs.byteregs[regah] + 1;

  1656.                         af = 1;

  1657.                         cf = 1;

  1658.                     }

  1659.                 else {

  1660.                         af = 0;

  1661.                         cf = 0;

  1662.                     }

  1663. 

  1664.                 regs.byteregs[regal] = regs.byteregs[regal] & 0xF;

  1665.                 break;

  1666. 

  1667.             case 0x38:	/* 38 CMP Eb Gb */

  1668.                 modregrm();

  1669.                 oper1b = readrm8 (rm);

  1670.                 oper2b = getreg8 (reg);

  1671.                 flag_sub8 (oper1b, oper2b);

  1672.                 break;

  1673. 

  1674.             case 0x39:	/* 39 CMP Ev Gv */

  1675.                 modregrm();

  1676.                 oper1 = readrm16 (rm);

  1677.                 oper2 = getreg16 (reg);

  1678.                 flag_sub16 (oper1, oper2);

  1679.                 break;

  1680. 

  1681.             case 0x3A:	/* 3A CMP Gb Eb */

  1682.                 modregrm();

  1683.                 oper1b = getreg8 (reg);

  1684.                 oper2b = readrm8 (rm);

  1685.                 flag_sub8 (oper1b, oper2b);

  1686.                 break;

  1687. 

  1688.             case 0x3B:	/* 3B CMP Gv Ev */

  1689.                 modregrm();

  1690.                 oper1 = getreg16 (reg);

  1691.                 oper2 = readrm16 (rm);

  1692.                 flag_sub16 (oper1, oper2);

  1693.                 break;

  1694. 

  1695.             case 0x3C:	/* 3C CMP regs.byteregs[regal] Ib */

  1696.                 oper1b = regs.byteregs[regal];

  1697.                 oper2b = getmem8 (segregs[regcs], ip);

  1698.                 StepIP (1);

  1699.                 flag_sub8 (oper1b, oper2b);

  1700.                 break;

  1701. 

  1702.             case 0x3D:	/* 3D CMP eAX Iv */

  1703.                 oper1 = regs.wordregs[regax];

  1704.                 oper2 = getmem16 (segregs[regcs], ip);

  1705.                 StepIP (2);

  1706.                 flag_sub16 (oper1, oper2);

  1707.                 break;

  1708. 

  1709.             case 0x3F:	/* 3F AAS ASCII */

  1710.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1711.                         regs.byteregs[regal] = regs.byteregs[regal] - 6;

  1712.                         regs.byteregs[regah] = regs.byteregs[regah] - 1;

  1713.                         af = 1;

  1714.                         cf = 1;

  1715.                     }

  1716.                 else {

  1717.                         af = 0;

  1718.                         cf = 0;

  1719.                     }

  1720. 

  1721.                 regs.byteregs[regal] = regs.byteregs[regal] & 0xF;

  1722.                 break;

  1723. 

  1724.             case 0x40:	/* 40 INC eAX */

  1725.                 oldcf = cf;

  1726.                 oper1 = regs.wordregs[regax];

  1727.                 oper2 = 1;

  1728.                 op_add16();

  1729.                 cf = oldcf;

  1730.                 regs.wordregs[regax] = res16;

  1731.                 break;

  1732. 

  1733.             case 0x41:	/* 41 INC eCX */

  1734.                 oldcf = cf;

  1735.                 oper1 = regs.wordregs[regcx];

  1736.                 oper2 = 1;

  1737.                 op_add16();

  1738.                 cf = oldcf;

  1739.                 regs.wordregs[regcx] = res16;

  1740.                 break;

  1741. 

  1742.             case 0x42:	/* 42 INC eDX */

  1743.                 oldcf = cf;

  1744.                 oper1 = regs.wordregs[regdx];

  1745.                 oper2 = 1;

  1746.                 op_add16();

  1747.                 cf = oldcf;

  1748.                 regs.wordregs[regdx] = res16;

  1749.                 break;

  1750. 

  1751.             case 0x43:	/* 43 INC eBX */

  1752.                 oldcf = cf;

  1753.                 oper1 = regs.wordregs[regbx];

  1754.                 oper2 = 1;

  1755.                 op_add16();

  1756.                 cf = oldcf;

  1757.                 regs.wordregs[regbx] = res16;

  1758.                 break;

  1759. 

  1760.             case 0x44:	/* 44 INC eSP */

  1761.                 oldcf = cf;

  1762.                 oper1 = regs.wordregs[regsp];

  1763.                 oper2 = 1;

  1764.                 op_add16();

  1765.                 cf = oldcf;

  1766.                 regs.wordregs[regsp] = res16;

  1767.                 break;

  1768. 

  1769.             case 0x45:	/* 45 INC eBP */

  1770.                 oldcf = cf;

  1771.                 oper1 = regs.wordregs[regbp];

  1772.                 oper2 = 1;

  1773.                 op_add16();

  1774.                 cf = oldcf;

  1775.                 regs.wordregs[regbp] = res16;

  1776.                 break;

  1777. 

  1778.             case 0x46:	/* 46 INC eSI */

  1779.                 oldcf = cf;

  1780.                 oper1 = regs.wordregs[regsi];

  1781.                 oper2 = 1;

  1782.                 op_add16();

  1783.                 cf = oldcf;

  1784.                 regs.wordregs[regsi] = res16;

  1785.                 break;

  1786. 

  1787.             case 0x47:	/* 47 INC eDI */

  1788.                 oldcf = cf;

  1789.                 oper1 = regs.wordregs[regdi];

  1790.                 oper2 = 1;

  1791.                 op_add16();

  1792.                 cf = oldcf;

  1793.                 regs.wordregs[regdi] = res16;

  1794.                 break;

  1795. 

  1796.             case 0x48:	/* 48 DEC eAX */

  1797.                 oldcf = cf;

  1798.                 oper1 = regs.wordregs[regax];

  1799.                 oper2 = 1;

  1800.                 op_sub16();

  1801.                 cf = oldcf;

  1802.                 regs.wordregs[regax] = res16;

  1803.                 break;

  1804. 

  1805.             case 0x49:	/* 49 DEC eCX */

  1806.                 oldcf = cf;

  1807.                 oper1 = regs.wordregs[regcx];

  1808.                 oper2 = 1;

  1809.                 op_sub16();

  1810.                 cf = oldcf;

  1811.                 regs.wordregs[regcx] = res16;

  1812.                 break;

  1813. 

  1814.             case 0x4A:	/* 4A DEC eDX */

  1815.                 oldcf = cf;

  1816.                 oper1 = regs.wordregs[regdx];

  1817.                 oper2 = 1;

  1818.                 op_sub16();

  1819.                 cf = oldcf;

  1820.                 regs.wordregs[regdx] = res16;

  1821.                 break;

  1822. 

  1823.             case 0x4B:	/* 4B DEC eBX */

  1824.                 oldcf = cf;

  1825.                 oper1 = regs.wordregs[regbx];

  1826.                 oper2 = 1;

  1827.                 op_sub16();

  1828.                 cf = oldcf;

  1829.                 regs.wordregs[regbx] = res16;

  1830.                 break;

  1831. 

  1832.             case 0x4C:	/* 4C DEC eSP */

  1833.                 oldcf = cf;

  1834.                 oper1 = regs.wordregs[regsp];

  1835.                 oper2 = 1;

  1836.                 op_sub16();

  1837.                 cf = oldcf;

  1838.                 regs.wordregs[regsp] = res16;

  1839.                 break;

  1840. 

  1841.             case 0x4D:	/* 4D DEC eBP */

  1842.                 oldcf = cf;

  1843.                 oper1 = regs.wordregs[regbp];

  1844.                 oper2 = 1;

  1845.                 op_sub16();

  1846.                 cf = oldcf;

  1847.                 regs.wordregs[regbp] = res16;

  1848.                 break;

  1849. 

  1850.             case 0x4E:	/* 4E DEC eSI */

  1851.                 oldcf = cf;

  1852.                 oper1 = regs.wordregs[regsi];

  1853.                 oper2 = 1;

  1854.                 op_sub16();

  1855.                 cf = oldcf;

  1856.                 regs.wordregs[regsi] = res16;

  1857.                 break;

  1858. 

  1859.             case 0x4F:	/* 4F DEC eDI */

  1860.                 oldcf = cf;

  1861.                 oper1 = regs.wordregs[regdi];

  1862.                 oper2 = 1;

  1863.                 op_sub16();

  1864.                 cf = oldcf;

  1865.                 regs.wordregs[regdi] = res16;

  1866.                 break;

  1867. 

  1868.             case 0x50:	/* 50 PUSH eAX */

  1869.                 push (regs.wordregs[regax]);

  1870.                 break;

  1871. 

  1872.             case 0x51:	/* 51 PUSH eCX */

  1873.                 push (regs.wordregs[regcx]);

  1874.                 break;

  1875. 

  1876.             case 0x52:	/* 52 PUSH eDX */

  1877.                 push (regs.wordregs[regdx]);

  1878.                 break;

  1879. 

  1880.             case 0x53:	/* 53 PUSH eBX */

  1881.                 push (regs.wordregs[regbx]);

  1882.                 break;

  1883. 

  1884.             case 0x54:	/* 54 PUSH eSP */

  1885. #ifdef USE_286_STYLE_PUSH_SP

  1886.                 push (regs.wordregs[regsp]);

  1887. #else

  1888.                 push (regs.wordregs[regsp] - 2);

  1889. #endif

  1890.                 break;

  1891. 

  1892.             case 0x55:	/* 55 PUSH eBP */

  1893.                 push (regs.wordregs[regbp]);

  1894.                 break;

  1895. 

  1896.             case 0x56:	/* 56 PUSH eSI */

  1897.                 push (regs.wordregs[regsi]);

  1898.                 break;

  1899. 

  1900.             case 0x57:	/* 57 PUSH eDI */

  1901.                 push (regs.wordregs[regdi]);

  1902.                 break;

  1903. 

  1904.             case 0x58:	/* 58 POP eAX */

  1905.                 regs.wordregs[regax] = pop();

  1906.                 break;

  1907. 

  1908.             case 0x59:	/* 59 POP eCX */

  1909.                 regs.wordregs[regcx] = pop();

  1910.                 break;

  1911. 

  1912.             case 0x5A:	/* 5A POP eDX */

  1913.                 regs.wordregs[regdx] = pop();

  1914.                 break;

  1915. 

  1916.             case 0x5B:	/* 5B POP eBX */

  1917.                 regs.wordregs[regbx] = pop();

  1918.                 break;

  1919. 

  1920.             case 0x5C:	/* 5C POP eSP */

  1921.                 regs.wordregs[regsp] = pop();

  1922.                 break;

  1923. 

  1924.             case 0x5D:	/* 5D POP eBP */

  1925.                 regs.wordregs[regbp] = pop();

  1926.                 break;

  1927. 

  1928.             case 0x5E:	/* 5E POP eSI */

  1929.                 regs.wordregs[regsi] = pop();

  1930.                 break;

  1931. 

  1932.             case 0x5F:	/* 5F POP eDI */

  1933.                 regs.wordregs[regdi] = pop();

  1934.                 break;

  1935. 

  1936. #ifndef CPU_8086

  1937.             case 0x60:	/* 60 PUSHA (80186+) */

  1938.                 oldsp = regs.wordregs[regsp];

  1939.                 push (regs.wordregs[regax]);

  1940.                 push (regs.wordregs[regcx]);

  1941.                 push (regs.wordregs[regdx]);

  1942.                 push (regs.wordregs[regbx]);

  1943.                 push (oldsp);

  1944.                 push (regs.wordregs[regbp]);

  1945.                 push (regs.wordregs[regsi]);

  1946.                 push (regs.wordregs[regdi]);

  1947.                 break;

  1948. 

  1949.             case 0x61:	/* 61 POPA (80186+) */

  1950.                 regs.wordregs[regdi] = pop();

  1951.                 regs.wordregs[regsi] = pop();

  1952.                 regs.wordregs[regbp] = pop();

  1953.                 pop();

  1954.                 regs.wordregs[regbx] = pop();

  1955.                 regs.wordregs[regdx] = pop();

  1956.                 regs.wordregs[regcx] = pop();

  1957.                 regs.wordregs[regax] = pop();

  1958.                 break;

  1959. 

  1960.             case 0x62: /* 62 BOUND Gv, Ev (80186+) */

  1961.                 modregrm();

  1962.                 getea (rm);

  1963.                 if (signext32 (getreg16 (reg) ) < signext32 ( getmem16 (ea >> 4, ea & 15) ) ) {

  1964.                         intcall86 (5); //bounds check exception

  1965.                     }

  1966.                 else {

  1967.                         ea += 2;

  1968.                         if (signext32 (getreg16 (reg) ) > signext32 ( getmem16 (ea >> 4, ea & 15) ) ) {

  1969.                                 intcall86(5); //bounds check exception

  1970.                             }

  1971.                     }

  1972.                 break;

  1973. 

  1974.             case 0x68:	/* 68 PUSH Iv (80186+) */

  1975.                 push (getmem16 (segregs[regcs], ip) );

  1976.                 StepIP (2);

  1977.                 break;

  1978. 

  1979.             case 0x69:	/* 69 IMUL Gv Ev Iv (80186+) */

  1980.                 modregrm();

  1981.                 temp1 = readrm16 (rm);

  1982.                 temp2 = getmem16 (segregs[regcs], ip);

  1983.                 StepIP (2);

  1984.                 if ( (temp1 & 0x8000L) == 0x8000L) {

  1985.                         temp1 = temp1 | 0xFFFF0000L;

  1986.                     }

  1987. 

  1988.                 if ( (temp2 & 0x8000L) == 0x8000L) {

  1989.                         temp2 = temp2 | 0xFFFF0000L;

  1990.                     }

  1991. 

  1992.                 temp3 = temp1 * temp2;

  1993.                 putreg16 (reg, temp3 & 0xFFFFL);

  1994.                 if (temp3 & 0xFFFF0000L) {

  1995.                         cf = 1;

  1996.                         of = 1;

  1997.                     }

  1998.                 else {

  1999.                         cf = 0;

  2000.                         of = 0;

  2001.                     }

  2002.                 break;

  2003. 

  2004.             case 0x6A:	/* 6A PUSH Ib (80186+) */

  2005.                 push (getmem8 (segregs[regcs], ip) );

  2006.                 StepIP (1);

  2007.                 break;

  2008. 

  2009.             case 0x6B:	/* 6B IMUL Gv Eb Ib (80186+) */

  2010.                 modregrm();

  2011.                 temp1 = readrm16 (rm);

  2012.                 temp2 = signext (getmem8 (segregs[regcs], ip) );

  2013.                 StepIP (1);

  2014.                 if ( (temp1 & 0x8000L) == 0x8000L) {

  2015.                         temp1 = temp1 | 0xFFFF0000L;

  2016.                     }

  2017. 

  2018.                 if ( (temp2 & 0x8000L) == 0x8000L) {

  2019.                         temp2 = temp2 | 0xFFFF0000L;

  2020.                     }

  2021. 

  2022.                 temp3 = temp1 * temp2;

  2023.                 putreg16 (reg, temp3 & 0xFFFFL);

  2024.                 if (temp3 & 0xFFFF0000L) {

  2025.                         cf = 1;

  2026.                         of = 1;

  2027.                     }

  2028.                 else {

  2029.                         cf = 0;

  2030.                         of = 0;

  2031.                     }

  2032.                 break;

  2033. 

  2034.             case 0x6C:	/* 6E INSB */

  2035.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2036.                         break;

  2037.                     }

  2038. 

  2039.                 putmem8 (useseg, regs.wordregs[regsi], portin (regs.wordregs[regdx]) );

  2040.                 if (df) {

  2041.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2042.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2043.                     }

  2044.                 else {

  2045.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2046.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2047.                     }

  2048. 

  2049.                 if (reptype) {

  2050.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2051.                     }

  2052. 

  2053.                 loopcount++;

  2054.                 if (!reptype) {

  2055.                         break;

  2056.                     }

  2057. 

  2058.                 ip = firstip;

  2059.                 break;

  2060. 

  2061.             case 0x6D:	/* 6F INSW */

  2062.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2063.                         break;

  2064.                     }

  2065. 

  2066.                 putmem16 (useseg, regs.wordregs[regsi], portin16 (regs.wordregs[regdx]) );

  2067.                 if (df) {

  2068.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2069.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2070.                     }

  2071.                 else {

  2072.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2073.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2074.                     }

  2075. 

  2076.                 if (reptype) {

  2077.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2078.                     }

  2079. 

  2080.                 loopcount++;

  2081.                 if (!reptype) {

  2082.                         break;

  2083.                     }

  2084. 

  2085.                 ip = firstip;

  2086.                 break;

  2087. 

  2088.             case 0x6E:	/* 6E OUTSB */

  2089.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2090.                         break;

  2091.                     }

  2092. 

  2093.                 portout (regs.wordregs[regdx], getmem8 (useseg, regs.wordregs[regsi]) );

  2094.                 if (df) {

  2095.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2096.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2097.                     }

  2098.                 else {

  2099.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2100.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2101.                     }

  2102. 

  2103.                 if (reptype) {

  2104.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2105.                     }

  2106. 

  2107.                 loopcount++;

  2108.                 if (!reptype) {

  2109.                         break;

  2110.                     }

  2111. 

  2112.                 ip = firstip;

  2113.                 break;

  2114. 

  2115.             case 0x6F:	/* 6F OUTSW */

  2116.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2117.                         break;

  2118.                     }

  2119. 

  2120.                 portout16 (regs.wordregs[regdx], getmem16 (useseg, regs.wordregs[regsi]) );

  2121.                 if (df) {

  2122.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2123.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2124.                     }

  2125.                 else {

  2126.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2127.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2128.                     }

  2129. 

  2130.                 if (reptype) {

  2131.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2132.                     }

  2133. 

  2134.                 loopcount++;

  2135.                 if (!reptype) {

  2136.                         break;

  2137.                     }

  2138. 

  2139.                 ip = firstip;

  2140.                 break;

  2141. #endif

  2142. 

  2143.             case 0x70:	/* 70 JO Jb */

  2144.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2145.                 StepIP (1);

  2146.                 if (of) {

  2147.                         ip = ip + temp16;

  2148.                     }

  2149.                 break;

  2150. 

  2151.             case 0x71:	/* 71 JNO Jb */

  2152.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2153.                 StepIP (1);

  2154.                 if (!of) {

  2155.                         ip = ip + temp16;

  2156.                     }

  2157.                 break;

  2158. 

  2159.             case 0x72:	/* 72 JB Jb */

  2160.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2161.                 StepIP (1);

  2162.                 if (cf) {

  2163.                         ip = ip + temp16;

  2164.                     }

  2165.                 break;

  2166. 

  2167.             case 0x73:	/* 73 JNB Jb */

  2168.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2169.                 StepIP (1);

  2170.                 if (!cf) {

  2171.                         ip = ip + temp16;

  2172.                     }

  2173.                 break;

  2174. 

  2175.             case 0x74:	/* 74 JZ Jb */

  2176.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2177.                 StepIP (1);

  2178.                 if (zf) {

  2179.                         ip = ip + temp16;

  2180.                     }

  2181.                 break;

  2182. 

  2183.             case 0x75:	/* 75 JNZ Jb */

  2184.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2185.                 StepIP (1);

  2186.                 if (!zf) {

  2187.                         ip = ip + temp16;

  2188.                     }

  2189.                 break;

  2190. 

  2191.             case 0x76:	/* 76 JBE Jb */

  2192.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2193.                 StepIP (1);

  2194.                 if (cf || zf) {

  2195.                         ip = ip + temp16;

  2196.                     }

  2197.                 break;

  2198. 

  2199.             case 0x77:	/* 77 JA Jb */

  2200.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2201.                 StepIP (1);

  2202.                 if (!cf && !zf) {

  2203.                         ip = ip + temp16;

  2204.                     }

  2205.                 break;

  2206. 

  2207.             case 0x78:	/* 78 JS Jb */

  2208.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2209.                 StepIP (1);

  2210.                 if (sf) {

  2211.                         ip = ip + temp16;

  2212.                     }

  2213.                 break;

  2214. 

  2215.             case 0x79:	/* 79 JNS Jb */

  2216.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2217.                 StepIP (1);

  2218.                 if (!sf) {

  2219.                         ip = ip + temp16;

  2220.                     }

  2221.                 break;

  2222. 

  2223.             case 0x7A:	/* 7A JPE Jb */

  2224.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2225.                 StepIP (1);

  2226.                 if (pf) {

  2227.                         ip = ip + temp16;

  2228.                     }

  2229.                 break;

  2230. 

  2231.             case 0x7B:	/* 7B JPO Jb */

  2232.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2233.                 StepIP (1);

  2234.                 if (!pf) {

  2235.                         ip = ip + temp16;

  2236.                     }

  2237.                 break;

  2238. 

  2239.             case 0x7C:	/* 7C JL Jb */

  2240.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2241.                 StepIP (1);

  2242.                 if (sf != of) {

  2243.                         ip = ip + temp16;

  2244.                     }

  2245.                 break;

  2246. 

  2247.             case 0x7D:	/* 7D JGE Jb */

  2248.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2249.                 StepIP (1);

  2250.                 if (sf == of) {

  2251.                         ip = ip + temp16;

  2252.                     }

  2253.                 break;

  2254. 

  2255.             case 0x7E:	/* 7E JLE Jb */

  2256.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2257.                 StepIP (1);

  2258.                 if ( (sf != of) || zf) {

  2259.                         ip = ip + temp16;

  2260.                     }

  2261.                 break;

  2262. 

  2263.             case 0x7F:	/* 7F JG Jb */

  2264.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2265.                 StepIP (1);

  2266.                 if (!zf && (sf == of) ) {

  2267.                         ip = ip + temp16;

  2268.                     }

  2269.                 break;

  2270. 

  2271.             case 0x80:

  2272.             case 0x82:	/* 80/82 GRP1 Eb Ib */

  2273.                 modregrm();

  2274.                 oper1b = readrm8 (rm);

  2275.                 oper2b = getmem8 (segregs[regcs], ip);

  2276.                 StepIP (1);

  2277.                 switch (reg) {

  2278.                         case 0:

  2279.                             op_add8();

  2280.                             break;

  2281.                         case 1:

  2282.                             op_or8();

  2283.                             break;

  2284.                         case 2:

  2285.                             op_adc8();

  2286.                             break;

  2287.                         case 3:

  2288.                             op_sbb8();

  2289.                             break;

  2290.                         case 4:

  2291.                             op_and8();

  2292.                             break;

  2293.                         case 5:

  2294.                             op_sub8();

  2295.                             break;

  2296.                         case 6:

  2297.                             op_xor8();

  2298.                             break;

  2299.                         case 7:

  2300.                             flag_sub8 (oper1b, oper2b);

  2301.                             break;

  2302.                         default:

  2303.                             break;	/* to avoid compiler warnings */

  2304.                     }

  2305. 

  2306.                 if (reg < 7) {

  2307.                         writerm8 (rm, res8);

  2308.                     }

  2309.                 break;

  2310. 

  2311.             case 0x81:	/* 81 GRP1 Ev Iv */

  2312.             case 0x83:	/* 83 GRP1 Ev Ib */

  2313.                 modregrm();

  2314.                 oper1 = readrm16 (rm);

  2315.                 if (opcode == 0x81) {

  2316.                         oper2 = getmem16 (segregs[regcs], ip);

  2317.                         StepIP (2);

  2318.                     }

  2319.                 else {

  2320.                         oper2 = signext (getmem8 (segregs[regcs], ip) );

  2321.                         StepIP (1);

  2322.                     }

  2323. 

  2324.                 switch (reg) {

  2325.                         case 0:

  2326.                             op_add16();

  2327.                             break;

  2328.                         case 1:

  2329.                             op_or16();

  2330.                             break;

  2331.                         case 2:

  2332.                             op_adc16();

  2333.                             break;

  2334.                         case 3:

  2335.                             op_sbb16();

  2336.                             break;

  2337.                         case 4:

  2338.                             op_and16();

  2339.                             break;

  2340.                         case 5:

  2341.                             op_sub16();

  2342.                             break;

  2343.                         case 6:

  2344.                             op_xor16();

  2345.                             break;

  2346.                         case 7:

  2347.                             flag_sub16 (oper1, oper2);

  2348.                             break;

  2349.                         default:

  2350.                             break;	/* to avoid compiler warnings */

  2351.                     }

  2352. 

  2353.                 if (reg < 7) {

  2354.                         writerm16 (rm, res16);

  2355.                     }

  2356.                 break;

  2357. 

  2358.             case 0x84:	/* 84 TEST Gb Eb */

  2359.                 modregrm();

  2360.                 oper1b = getreg8 (reg);

  2361.                 oper2b = readrm8 (rm);

  2362.                 flag_log8 (oper1b & oper2b);

  2363.                 break;

  2364. 

  2365.             case 0x85:	/* 85 TEST Gv Ev */

  2366.                 modregrm();

  2367.                 oper1 = getreg16 (reg);

  2368.                 oper2 = readrm16 (rm);

  2369.                 flag_log16 (oper1 & oper2);

  2370.                 break;

  2371. 

  2372.             case 0x86:	/* 86 XCHG Gb Eb */

  2373.                 modregrm();

  2374.                 oper1b = getreg8 (reg);

  2375.                 putreg8 (reg, readrm8 (rm) );

  2376.                 writerm8 (rm, oper1b);

  2377.                 break;

  2378. 

  2379.             case 0x87:	/* 87 XCHG Gv Ev */

  2380.                 modregrm();

  2381.                 oper1 = getreg16 (reg);

  2382.                 putreg16 (reg, readrm16 (rm) );

  2383.                 writerm16 (rm, oper1);

  2384.                 break;

  2385. 

  2386.             case 0x88:	/* 88 MOV Eb Gb */

  2387.                 modregrm();

  2388.                 writerm8 (rm, getreg8 (reg) );

  2389.                 break;

  2390. 

  2391.             case 0x89:	/* 89 MOV Ev Gv */

  2392.                 modregrm();

  2393.                 writerm16 (rm, getreg16 (reg) );

  2394.                 break;

  2395. 

  2396.             case 0x8A:	/* 8A MOV Gb Eb */

  2397.                 modregrm();

  2398.                 putreg8 (reg, readrm8 (rm) );

  2399.                 break;

  2400. 

  2401.             case 0x8B:	/* 8B MOV Gv Ev */

  2402.                 modregrm();

  2403.                 putreg16 (reg, readrm16 (rm) );

  2404.                 break;

  2405. 

  2406.             case 0x8C:	/* 8C MOV Ew Sw */

  2407.                 modregrm();

  2408.                 writerm16 (rm, getsegreg (reg) );

  2409.                 break;

  2410. 

  2411.             case 0x8D:	/* 8D LEA Gv M */

  2412.                 modregrm();

  2413.                 getea (rm);

  2414.                 putreg16 (reg, ea - segbase (useseg) );

  2415.                 break;

  2416. 

  2417.             case 0x8E:	/* 8E MOV Sw Ew */

  2418.                 modregrm();

  2419.                 putsegreg (reg, readrm16 (rm) );

  2420.                 break;

  2421. 

  2422.             case 0x8F:	/* 8F POP Ev */

  2423.                 modregrm();

  2424.                 writerm16 (rm, pop() );

  2425.                 break;

  2426. 

  2427.             case 0x90:	/* 90 NOP */

  2428.                 break;

  2429. 

  2430.             case 0x91:	/* 91 XCHG eCX eAX */

  2431.                 oper1 = regs.wordregs[regcx];

  2432.                 regs.wordregs[regcx] = regs.wordregs[regax];

  2433.                 regs.wordregs[regax] = oper1;

  2434.                 break;

  2435. 

  2436.             case 0x92:	/* 92 XCHG eDX eAX */

  2437.                 oper1 = regs.wordregs[regdx];

  2438.                 regs.wordregs[regdx] = regs.wordregs[regax];

  2439.                 regs.wordregs[regax] = oper1;

  2440.                 break;

  2441. 

  2442.             case 0x93:	/* 93 XCHG eBX eAX */

  2443.                 oper1 = regs.wordregs[regbx];

  2444.                 regs.wordregs[regbx] = regs.wordregs[regax];

  2445.                 regs.wordregs[regax] = oper1;

  2446.                 break;

  2447. 

  2448.             case 0x94:	/* 94 XCHG eSP eAX */

  2449.                 oper1 = regs.wordregs[regsp];

  2450.                 regs.wordregs[regsp] = regs.wordregs[regax];

  2451.                 regs.wordregs[regax] = oper1;

  2452.                 break;

  2453. 

  2454.             case 0x95:	/* 95 XCHG eBP eAX */

  2455.                 oper1 = regs.wordregs[regbp];

  2456.                 regs.wordregs[regbp] = regs.wordregs[regax];

  2457.                 regs.wordregs[regax] = oper1;

  2458.                 break;

  2459. 

  2460.             case 0x96:	/* 96 XCHG eSI eAX */

  2461.                 oper1 = regs.wordregs[regsi];

  2462.                 regs.wordregs[regsi] = regs.wordregs[regax];

  2463.                 regs.wordregs[regax] = oper1;

  2464.                 break;

  2465. 

  2466.             case 0x97:	/* 97 XCHG eDI eAX */

  2467.                 oper1 = regs.wordregs[regdi];

  2468.                 regs.wordregs[regdi] = regs.wordregs[regax];

  2469.                 regs.wordregs[regax] = oper1;

  2470.                 break;

  2471. 

  2472.             case 0x98:	/* 98 CBW */

  2473.                 if ( (regs.byteregs[regal] & 0x80) == 0x80) {

  2474.                         regs.byteregs[regah] = 0xFF;

  2475.                     }

  2476.                 else {

  2477.                         regs.byteregs[regah] = 0;

  2478.                     }

  2479.                 break;

  2480. 

  2481.             case 0x99:	/* 99 CWD */

  2482.                 if ( (regs.byteregs[regah] & 0x80) == 0x80) {

  2483.                         regs.wordregs[regdx] = 0xFFFF;

  2484.                     }

  2485.                 else {

  2486.                         regs.wordregs[regdx] = 0;

  2487.                     }

  2488.                 break;

  2489. 

  2490.             case 0x9A:	/* 9A CALL Ap */

  2491.                 oper1 = getmem16 (segregs[regcs], ip);

  2492.                 StepIP (2);

  2493.                 oper2 = getmem16 (segregs[regcs], ip);

  2494.                 StepIP (2);

  2495.                 push (segregs[regcs]);

  2496.                 push (ip);

  2497.                 ip = oper1;

  2498.                 segregs[regcs] = oper2;

  2499.                 break;

  2500. 

  2501.             case 0x9B:	/* 9B WAIT */

  2502.                 break;

  2503. 

  2504.             case 0x9C:	/* 9C PUSHF */

  2505.                 push (makeflagsword() | 0xF800);

  2506.                 break;

  2507. 

  2508.             case 0x9D:	/* 9D POPF */

  2509.                 decodeflagsword (pop());

  2510.                 break;

  2511. 

  2512.             case 0x9E:	/* 9E SAHF */

  2513.                 decodeflagsword ( (makeflagsword() & 0xFF00) | regs.byteregs[regah]);

  2514.                 break;

  2515. 

  2516.             case 0x9F:	/* 9F LAHF */

  2517.                 regs.byteregs[regah] = makeflagsword() & 0xFF;

  2518.                 break;

  2519. 

  2520.             case 0xA0:	/* A0 MOV regs.byteregs[regal] Ob */

  2521.                 regs.byteregs[regal] = getmem8 (useseg, getmem16 (segregs[regcs], ip) );

  2522.                 StepIP (2);

  2523.                 break;

  2524. 

  2525.             case 0xA1:	/* A1 MOV eAX Ov */

  2526.                 oper1 = getmem16 (useseg, getmem16 (segregs[regcs], ip) );

  2527.                 StepIP (2);

  2528.                 regs.wordregs[regax] = oper1;

  2529.                 break;

  2530. 

  2531.             case 0xA2:	/* A2 MOV Ob regs.byteregs[regal] */

  2532.                 putmem8 (useseg, getmem16 (segregs[regcs], ip), regs.byteregs[regal]);

  2533.                 StepIP (2);

  2534.                 break;

  2535. 

  2536.             case 0xA3:	/* A3 MOV Ov eAX */

  2537.                 putmem16 (useseg, getmem16 (segregs[regcs], ip), regs.wordregs[regax]);

  2538.                 StepIP (2);

  2539.                 break;

  2540. 

  2541.             case 0xA4:	/* A4 MOVSB */

  2542.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2543.                         break;

  2544.                     }

  2545. 

  2546.                 putmem8 (segregs[reges], regs.wordregs[regdi], getmem8 (useseg, regs.wordregs[regsi]) );

  2547.                 if (df) {

  2548.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2549.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2550.                     }

  2551.                 else {

  2552.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2553.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2554.                     }

  2555. 

  2556.                 if (reptype) {

  2557.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2558.                     }

  2559. 

  2560.                 loopcount++;

  2561.                 if (!reptype) {

  2562.                         break;

  2563.                     }

  2564. 

  2565.                 ip = firstip;

  2566.                 break;

  2567. 

  2568.             case 0xA5:	/* A5 MOVSW */

  2569.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2570.                         break;

  2571.                     }

  2572. 

  2573.                 putmem16 (segregs[reges], regs.wordregs[regdi], getmem16 (useseg, regs.wordregs[regsi]) );

  2574.                 if (df) {

  2575.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2576.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2577.                     }

  2578.                 else {

  2579.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2580.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2581.                     }

  2582. 

  2583.                 if (reptype) {

  2584.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2585.                     }

  2586. 

  2587.                 loopcount++;

  2588.                 if (!reptype) {

  2589.                         break;

  2590.                     }

  2591. 

  2592.                 ip = firstip;

  2593.                 break;

  2594. 

  2595.             case 0xA6:	/* A6 CMPSB */

  2596.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2597.                         break;

  2598.                     }

  2599. 

  2600.                 oper1b = getmem8 (useseg, regs.wordregs[regsi]);

  2601.                 oper2b = getmem8 (segregs[reges], regs.wordregs[regdi]);

  2602.                 if (df) {

  2603.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2604.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2605.                     }

  2606.                 else {

  2607.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2608.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2609.                     }

  2610. 

  2611.                 flag_sub8 (oper1b, oper2b);

  2612.                 if (reptype) {

  2613.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2614.                     }

  2615. 

  2616.                 if ( (reptype == 1) && !zf) {

  2617.                         break;

  2618.                     }

  2619.                 else if ( (reptype == 2) && (zf == 1) ) {

  2620.                         break;

  2621.                     }

  2622. 

  2623.                 loopcount++;

  2624.                 if (!reptype) {

  2625.                         break;

  2626.                     }

  2627. 

  2628.                 ip = firstip;

  2629.                 break;

  2630. 

  2631.             case 0xA7:	/* A7 CMPSW */

  2632.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2633.                         break;

  2634.                     }

  2635. 

  2636.                 oper1 = getmem16 (useseg,regs.wordregs[regsi]);

  2637.                 oper2 = getmem16 (segregs[reges], regs.wordregs[regdi]);

  2638.                 if (df) {

  2639.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2640.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2641.                     }

  2642.                 else {

  2643.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2644.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2645.                     }

  2646. 

  2647.                 flag_sub16 (oper1, oper2);

  2648.                 if (reptype) {

  2649.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2650.                     }

  2651. 

  2652.                 if ( (reptype == 1) && !zf) {

  2653.                         break;

  2654.                     }

  2655. 

  2656.                 if ( (reptype == 2) && (zf == 1) ) {

  2657.                         break;

  2658.                     }

  2659. 

  2660.                 loopcount++;

  2661.                 if (!reptype) {

  2662.                         break;

  2663.                     }

  2664. 

  2665.                 ip = firstip;

  2666.                 break;

  2667. 

  2668.             case 0xA8:	/* A8 TEST regs.byteregs[regal] Ib */

  2669.                 oper1b = regs.byteregs[regal];

  2670.                 oper2b = getmem8 (segregs[regcs], ip);

  2671.                 StepIP (1);

  2672.                 flag_log8 (oper1b & oper2b);

  2673.                 break;

  2674. 

  2675.             case 0xA9:	/* A9 TEST eAX Iv */

  2676.                 oper1 = regs.wordregs[regax];

  2677.                 oper2 = getmem16 (segregs[regcs], ip);

  2678.                 StepIP (2);

  2679.                 flag_log16 (oper1 & oper2);

  2680.                 break;

  2681. 

  2682.             case 0xAA:	/* AA STOSB */

  2683.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2684.                         break;

  2685.                     }

  2686. 

  2687.                 putmem8 (segregs[reges], regs.wordregs[regdi], regs.byteregs[regal]);

  2688.                 if (df) {

  2689.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2690.                     }

  2691.                 else {

  2692.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2693.                     }

  2694. 

  2695.                 if (reptype) {

  2696.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2697.                     }

  2698. 

  2699.                 loopcount++;

  2700.                 if (!reptype) {

  2701.                         break;

  2702.                     }

  2703. 

  2704.                 ip = firstip;

  2705.                 break;

  2706. 

  2707.             case 0xAB:	/* AB STOSW */

  2708.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2709.                         break;

  2710.                     }

  2711. 

  2712.                 putmem16 (segregs[reges], regs.wordregs[regdi], regs.wordregs[regax]);

  2713.                 if (df) {

  2714.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2715.                     }

  2716.                 else {

  2717.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2718.                     }

  2719. 

  2720.                 if (reptype) {

  2721.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2722.                     }

  2723. 

  2724.                 loopcount++;

  2725.                 if (!reptype) {

  2726.                         break;

  2727.                     }

  2728. 

  2729.                 ip = firstip;

  2730.                 break;

  2731. 

  2732.             case 0xAC:	/* AC LODSB */

  2733.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2734.                         break;

  2735.                     }

  2736. 

  2737.                 regs.byteregs[regal] = getmem8 (useseg, regs.wordregs[regsi]);

  2738.                 if (df) {

  2739.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2740.                     }

  2741.                 else {

  2742.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2743.                     }

  2744. 

  2745.                 if (reptype) {

  2746.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2747.                     }

  2748. 

  2749.                 loopcount++;

  2750.                 if (!reptype) {

  2751.                         break;

  2752.                     }

  2753. 

  2754.                 ip = firstip;

  2755.                 break;

  2756. 

  2757.             case 0xAD:	/* AD LODSW */

  2758.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2759.                         break;

  2760.                     }

  2761. 

  2762.                 oper1 = getmem16 (useseg, regs.wordregs[regsi]);

  2763.                 regs.wordregs[regax] = oper1;

  2764.                 if (df) {

  2765.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2766.                     }

  2767.                 else {

  2768.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2769.                     }

  2770. 

  2771.                 if (reptype) {

  2772.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2773.                     }

  2774. 

  2775.                 loopcount++;

  2776.                 if (!reptype) {

  2777.                         break;

  2778.                     }

  2779. 

  2780.                 ip = firstip;

  2781.                 break;

  2782. 

  2783.             case 0xAE:	/* AE SCASB */

  2784.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2785.                         break;

  2786.                     }

  2787. 

  2788.                 oper1b = regs.byteregs[regal];

  2789.                 oper2b = getmem8 (segregs[reges], regs.wordregs[regdi]);

  2790.                 flag_sub8 (oper1b, oper2b);

  2791.                 if (df) {

  2792.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2793.                     }

  2794.                 else {

  2795.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2796.                     }

  2797. 

  2798.                 if (reptype) {

  2799.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2800.                     }

  2801. 

  2802.                 if ( (reptype == 1) && !zf) {

  2803.                         break;

  2804.                     }

  2805.                 else if ( (reptype == 2) && (zf == 1) ) {

  2806.                         break;

  2807.                     }

  2808. 

  2809.                 loopcount++;

  2810.                 if (!reptype) {

  2811.                         break;

  2812.                     }

  2813. 

  2814.                 ip = firstip;

  2815.                 break;

  2816. 

  2817.             case 0xAF:	/* AF SCASW */

  2818.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2819.                         break;

  2820.                     }

  2821. 

  2822.                 oper1 = regs.wordregs[regax];

  2823.                 oper2 = getmem16 (segregs[reges], regs.wordregs[regdi]);

  2824.                 flag_sub16 (oper1, oper2);

  2825.                 if (df) {

  2826.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2827.                     }

  2828.                 else {

  2829.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2830.                     }

  2831. 

  2832.                 if (reptype) {

  2833.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2834.                     }

  2835. 

  2836.                 if ( (reptype == 1) && !zf) {

  2837.                         break;

  2838.                     }

  2839.                 else if ( (reptype == 2) & (zf == 1) ) {

  2840.                         break;

  2841.                     }

  2842. 

  2843.                 loopcount++;

  2844.                 if (!reptype) {

  2845.                         break;

  2846.                     }

  2847. 

  2848.                 ip = firstip;

  2849.                 break;

  2850. 

  2851.             case 0xB0:	/* B0 MOV regs.byteregs[regal] Ib */

  2852.                 regs.byteregs[regal] = getmem8 (segregs[regcs], ip);

  2853.                 StepIP (1);

  2854.                 break;

  2855. 

  2856.             case 0xB1:	/* B1 MOV regs.byteregs[regcl] Ib */

  2857.                 regs.byteregs[regcl] = getmem8 (segregs[regcs], ip);

  2858.                 StepIP (1);

  2859.                 break;

  2860. 

  2861.             case 0xB2:	/* B2 MOV regs.byteregs[regdl] Ib */

  2862.                 regs.byteregs[regdl] = getmem8 (segregs[regcs], ip);

  2863.                 StepIP (1);

  2864.                 break;

  2865. 

  2866.             case 0xB3:	/* B3 MOV regs.byteregs[regbl] Ib */

  2867.                 regs.byteregs[regbl] = getmem8 (segregs[regcs], ip);

  2868.                 StepIP (1);

  2869.                 break;

  2870. 

  2871.             case 0xB4:	/* B4 MOV regs.byteregs[regah] Ib */

  2872.                 regs.byteregs[regah] = getmem8 (segregs[regcs], ip);

  2873.                 StepIP (1);

  2874.                 break;

  2875. 

  2876.             case 0xB5:	/* B5 MOV regs.byteregs[regch] Ib */

  2877.                 regs.byteregs[regch] = getmem8 (segregs[regcs], ip);

  2878.                 StepIP (1);

  2879.                 break;

  2880. 

  2881.             case 0xB6:	/* B6 MOV regs.byteregs[regdh] Ib */

  2882.                 regs.byteregs[regdh] = getmem8 (segregs[regcs], ip);

  2883.                 StepIP (1);

  2884.                 break;

  2885. 

  2886.             case 0xB7:	/* B7 MOV regs.byteregs[regbh] Ib */

  2887.                 regs.byteregs[regbh] = getmem8 (segregs[regcs], ip);

  2888.                 StepIP (1);

  2889.                 break;

  2890. 

  2891.             case 0xB8:	/* B8 MOV eAX Iv */

  2892.                 oper1 = getmem16 (segregs[regcs], ip);

  2893.                 StepIP (2);

  2894.                 regs.wordregs[regax] = oper1;

  2895.                 break;

  2896. 

  2897.             case 0xB9:	/* B9 MOV eCX Iv */

  2898.                 oper1 = getmem16 (segregs[regcs], ip);

  2899.                 StepIP (2);

  2900.                 regs.wordregs[regcx] = oper1;

  2901.                 break;

  2902. 

  2903.             case 0xBA:	/* BA MOV eDX Iv */

  2904.                 oper1 = getmem16 (segregs[regcs], ip);

  2905.                 StepIP (2);

  2906.                 regs.wordregs[regdx] = oper1;

  2907.                 break;

  2908. 

  2909.             case 0xBB:	/* BB MOV eBX Iv */

  2910.                 oper1 = getmem16 (segregs[regcs], ip);

  2911.                 StepIP (2);

  2912.                 regs.wordregs[regbx] = oper1;

  2913.                 break;

  2914. 

  2915.             case 0xBC:	/* BC MOV eSP Iv */

  2916.                 regs.wordregs[regsp] = getmem16 (segregs[regcs], ip);

  2917.                 StepIP (2);

  2918.                 break;

  2919. 

  2920.             case 0xBD:	/* BD MOV eBP Iv */

  2921.                 regs.wordregs[regbp] = getmem16 (segregs[regcs], ip);

  2922.                 StepIP (2);

  2923.                 break;

  2924. 

  2925.             case 0xBE:	/* BE MOV eSI Iv */

  2926.                 regs.wordregs[regsi] = getmem16 (segregs[regcs], ip);

  2927.                 StepIP (2);

  2928.                 break;

  2929. 

  2930.             case 0xBF:	/* BF MOV eDI Iv */

  2931.                 regs.wordregs[regdi] = getmem16 (segregs[regcs], ip);

  2932.                 StepIP (2);

  2933.                 break;

  2934. 

  2935.             case 0xC0:	/* C0 GRP2 byte imm8 (80186+) */

  2936.                 modregrm();

  2937.                 oper1b = readrm8 (rm);

  2938.                 oper2b = getmem8 (segregs[regcs], ip);

  2939.                 StepIP (1);

  2940.                 writerm8 (rm, op_grp2_8 (oper2b) );

  2941.                 break;

  2942. 

  2943.             case 0xC1:	/* C1 GRP2 word imm8 (80186+) */

  2944.                 modregrm();

  2945.                 oper1 = readrm16 (rm);

  2946.                 oper2 = getmem8 (segregs[regcs], ip);

  2947.                 StepIP (1);

  2948.                 writerm16 (rm, op_grp2_16 ( (uint8_t) oper2) );

  2949.                 break;

  2950. 

  2951.             case 0xC2:	/* C2 RET Iw */

  2952.                 oper1 = getmem16 (segregs[regcs], ip);

  2953.                 ip = pop();

  2954.                 regs.wordregs[regsp] = regs.wordregs[regsp] + oper1;

  2955.                 break;

  2956. 

  2957.             case 0xC3:	/* C3 RET */

  2958.                 ip = pop();

  2959.                 break;

  2960. 

  2961.             case 0xC4:	/* C4 LES Gv Mp */

  2962.                 modregrm();

  2963.                 getea (rm);

  2964.                 putreg16 (reg, read86 (ea) + read86 (ea + 1) * 256);

  2965.                 segregs[reges] = read86 (ea + 2) + read86 (ea + 3) * 256;

  2966.                 break;

  2967. 

  2968.             case 0xC5:	/* C5 LDS Gv Mp */

  2969.                 modregrm();

  2970.                 getea (rm);

  2971.                 putreg16 (reg, read86 (ea) + read86 (ea + 1) * 256);

  2972.                 segregs[regds] = read86 (ea + 2) + read86 (ea + 3) * 256;

  2973.                 break;

  2974. 

  2975.             case 0xC6:	/* C6 MOV Eb Ib */

  2976.                 modregrm();

  2977.                 writerm8 (rm, getmem8 (segregs[regcs], ip) );

  2978.                 StepIP (1);

  2979.                 break;

  2980. 

  2981.             case 0xC7:	/* C7 MOV Ev Iv */

  2982.                 modregrm();

  2983.                 writerm16 (rm, getmem16 (segregs[regcs], ip) );

  2984.                 StepIP (2);

  2985.                 break;

  2986. 

  2987.             case 0xC8:	/* C8 ENTER (80186+) */

  2988.                 stacksize = getmem16 (segregs[regcs], ip);

  2989.                 StepIP (2);

  2990.                 nestlev = getmem8 (segregs[regcs], ip);

  2991.                 StepIP (1);

  2992.                 push (regs.wordregs[regbp]);

  2993.                 frametemp = regs.wordregs[regsp];

  2994.                 if (nestlev) {

  2995.                         for (temp16 = 1; temp16 < nestlev; temp16++) {

  2996.                                 regs.wordregs[regbp] = regs.wordregs[regbp] - 2;

  2997.                                 push (regs.wordregs[regbp]);

  2998.                             }

  2999. 

  3000.                         push (regs.wordregs[regsp]);

  3001.                     }

  3002. 

  3003.                 regs.wordregs[regbp] = frametemp;

  3004.                 regs.wordregs[regsp] = regs.wordregs[regbp] - stacksize;

  3005. 

  3006.                 break;

  3007. 

  3008.             case 0xC9:	/* C9 LEAVE (80186+) */

  3009.                 regs.wordregs[regsp] = regs.wordregs[regbp];

  3010.                 regs.wordregs[regbp] = pop();

  3011.                 break;

  3012. 

  3013.             case 0xCA:	/* CA RETF Iw */

  3014.                 oper1 = getmem16 (segregs[regcs], ip);

  3015.                 ip = pop();

  3016.                 segregs[regcs] = pop();

  3017.                 regs.wordregs[regsp] = regs.wordregs[regsp] + oper1;

  3018.                 break;

  3019. 

  3020.             case 0xCB:	/* CB RETF */

  3021.                 ip = pop();;

  3022.                 segregs[regcs] = pop();

  3023.                 break;

  3024. 

  3025.             case 0xCC:	/* CC INT 3 */

  3026.                 intcall86 (3);

  3027.                 break;

  3028. 

  3029.             case 0xCD:	/* CD INT Ib */

  3030.                 oper1b = getmem8 (segregs[regcs], ip);

  3031.                 StepIP (1);

  3032.                 intcall86 (oper1b);

  3033.                 break;

  3034. 

  3035.             case 0xCE:	/* CE INTO */

  3036.                 if (of) {

  3037.                         intcall86 (4);

  3038.                     }

  3039.                 break;

  3040. 

  3041.             case 0xCF:	/* CF IRET */

  3042.                 ip = pop();

  3043.                 segregs[regcs] = pop();

  3044.                 decodeflagsword (pop() );

  3045. 

  3046.                 /*

  3047.                  * if (net.enabled) net.canrecv = 1;

  3048.                  */

  3049.                 break;

  3050. 

  3051.             case 0xD0:	/* D0 GRP2 Eb 1 */

  3052.                 modregrm();

  3053.                 oper1b = readrm8 (rm);

  3054.                 writerm8 (rm, op_grp2_8 (1) );

  3055.                 break;

  3056. 

  3057.             case 0xD1:	/* D1 GRP2 Ev 1 */

  3058.                 modregrm();

  3059.                 oper1 = readrm16 (rm);

  3060.                 writerm16 (rm, op_grp2_16 (1) );

  3061.                 break;

  3062. 

  3063.             case 0xD2:	/* D2 GRP2 Eb regs.byteregs[regcl] */

  3064.                 modregrm();

  3065.                 oper1b = readrm8 (rm);

  3066.                 writerm8 (rm, op_grp2_8 (regs.byteregs[regcl]) );

  3067.                 break;

  3068. 

  3069.             case 0xD3:	/* D3 GRP2 Ev regs.byteregs[regcl] */

  3070.                 modregrm();

  3071.                 oper1 = readrm16 (rm);

  3072.                 writerm16 (rm, op_grp2_16 (regs.byteregs[regcl]) );

  3073.                 break;

  3074. 

  3075.             case 0xD4:	/* D4 AAM I0 */

  3076.                 oper1 = getmem8 (segregs[regcs], ip);

  3077.                 StepIP (1);

  3078.                 if (!oper1) {

  3079.                         intcall86 (0);

  3080.                         break;

  3081.                     }	/* division by zero */

  3082. 

  3083.                 regs.byteregs[regah] = (regs.byteregs[regal] / oper1) & 255;

  3084.                 regs.byteregs[regal] = (regs.byteregs[regal] % oper1) & 255;

  3085.                 flag_szp16 (regs.wordregs[regax]);

  3086.                 break;

  3087. 

  3088.             case 0xD5:	/* D5 AAD I0 */

  3089.                 oper1 = getmem8 (segregs[regcs], ip);

  3090.                 StepIP (1);

  3091.                 regs.byteregs[regal] = (regs.byteregs[regah] * oper1 + regs.byteregs[regal]) & 255;

  3092.                 regs.byteregs[regah] = 0;

  3093.                 flag_szp16 (regs.byteregs[regah] * oper1 + regs.byteregs[regal]);

  3094.                 sf = 0;

  3095.                 break;

  3096. 

  3097.             case 0xD6:	/* D6 XLAT on V20/V30, SALC on 8086/8088 */

  3098.             case 0xD7:	/* D7 XLAT */

  3099.                 regs.byteregs[regal] = read86(useseg * 16 + (regs.wordregs[regbx]) + regs.byteregs[regal]);

  3100.                 break;

  3101. 

  3102.             case 0xD8:

  3103.             case 0xD9:

  3104.             case 0xDA:

  3105.             case 0xDB:

  3106.             case 0xDC:

  3107.             case 0xDE:

  3108.             case 0xDD:

  3109.             case 0xDF:	/* escape to x87 FPU (unsupported) */

  3110.                 modregrm();

  3111.                 break;

  3112. 

  3113.             case 0xE0:	/* E0 LOOPNZ Jb */

  3114.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3115.                 StepIP (1);

  3116.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3117.                 if ( (regs.wordregs[regcx]) && !zf) {

  3118.                         ip = ip + temp16;

  3119.                     }

  3120.                 break;

  3121. 

  3122.             case 0xE1:	/* E1 LOOPZ Jb */

  3123.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3124.                 StepIP (1);

  3125.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3126.                 if (regs.wordregs[regcx] && (zf == 1) ) {

  3127.                         ip = ip + temp16;

  3128.                     }

  3129.                 break;

  3130. 

  3131.             case 0xE2:	/* E2 LOOP Jb */

  3132.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3133.                 StepIP (1);

  3134.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3135.                 if (regs.wordregs[regcx]) {

  3136.                         ip = ip + temp16;

  3137.                     }

  3138.                 break;

  3139. 

  3140.             case 0xE3:	/* E3 JCXZ Jb */

  3141.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3142.                 StepIP (1);

  3143.                 if (!regs.wordregs[regcx]) {

  3144.                         ip = ip + temp16;

  3145.                     }

  3146.                 break;

  3147. 

  3148.             case 0xE4:	/* E4 IN regs.byteregs[regal] Ib */

  3149.                 oper1b = getmem8 (segregs[regcs], ip);

  3150.                 StepIP (1);

  3151.                 regs.byteregs[regal] = (uint8_t) portin (oper1b);

  3152.                 break;

  3153. 

  3154.             case 0xE5:	/* E5 IN eAX Ib */

  3155.                 oper1b = getmem8 (segregs[regcs], ip);

  3156.                 StepIP (1);

  3157.                 regs.wordregs[regax] = portin16 (oper1b);

  3158.                 break;

  3159. 

  3160.             case 0xE6:	/* E6 OUT Ib regs.byteregs[regal] */

  3161.                 oper1b = getmem8 (segregs[regcs], ip);

  3162.                 StepIP (1);

  3163.                 portout (oper1b, regs.byteregs[regal]);

  3164.                 break;

  3165. 

  3166.             case 0xE7:	/* E7 OUT Ib eAX */

  3167.                 oper1b = getmem8 (segregs[regcs], ip);

  3168.                 StepIP (1);

  3169.                 portout16 (oper1b, regs.wordregs[regax]);

  3170.                 break;

  3171. 

  3172.             case 0xE8:	/* E8 CALL Jv */

  3173.                 oper1 = getmem16 (segregs[regcs], ip);

  3174.                 StepIP (2);

  3175.                 push (ip);

  3176.                 ip = ip + oper1;

  3177.                 break;

  3178. 

  3179.             case 0xE9:	/* E9 JMP Jv */

  3180.                 oper1 = getmem16 (segregs[regcs], ip);

  3181.                 StepIP (2);

  3182.                 ip = ip + oper1;

  3183.                 break;

  3184. 

  3185.             case 0xEA:	/* EA JMP Ap */

  3186.                 oper1 = getmem16 (segregs[regcs], ip);

  3187.                 StepIP (2);

  3188.                 oper2 = getmem16 (segregs[regcs], ip);

  3189.                 ip = oper1;

  3190.                 segregs[regcs] = oper2;

  3191.                 break;

  3192. 

  3193.             case 0xEB:	/* EB JMP Jb */

  3194.                 oper1 = signext (getmem8 (segregs[regcs], ip) );

  3195.                 StepIP (1);

  3196.                 ip = ip + oper1;

  3197.                 break;

  3198. 

  3199.             case 0xEC:	/* EC IN regs.byteregs[regal] regdx */

  3200.                 oper1 = regs.wordregs[regdx];

  3201.                 regs.byteregs[regal] = (uint8_t) portin (oper1);

  3202.                 break;

  3203. 

  3204.             case 0xED:	/* ED IN eAX regdx */

  3205.                 oper1 = regs.wordregs[regdx];

  3206.                 regs.wordregs[regax] = portin16 (oper1);

  3207.                 break;

  3208. 

  3209.             case 0xEE:	/* EE OUT regdx regs.byteregs[regal] */

  3210.                 oper1 = regs.wordregs[regdx];

  3211.                 portout (oper1, regs.byteregs[regal]);

  3212.                 break;

  3213. 

  3214.             case 0xEF:	/* EF OUT regdx eAX */

  3215.                 oper1 = regs.wordregs[regdx];

  3216.                 portout16 (oper1, regs.wordregs[regax]);

  3217.                 break;

  3218. 

  3219.             case 0xF0:	/* F0 LOCK */

  3220.                 break;

  3221. 

  3222.             case 0xF4:	/* F4 HLT */

  3223.                 hltstate = 1;

  3224.                 break;

  3225. 

  3226.             case 0xF5:	/* F5 CMC */

  3227.                 if (!cf) {

  3228.                         cf = 1;

  3229.                     }

  3230.                 else {

  3231.                         cf = 0;

  3232.                     }

  3233.                 break;

  3234. 

  3235.             case 0xF6:	/* F6 GRP3a Eb */

  3236.                 modregrm();

  3237.                 oper1b = readrm8 (rm);

  3238.                 op_grp3_8();

  3239.                 if ( (reg > 1) && (reg < 4) ) {

  3240.                         writerm8 (rm, res8);

  3241.                     }

  3242.                 break;

  3243. 

  3244.             case 0xF7:	/* F7 GRP3b Ev */

  3245.                 modregrm();

  3246.                 oper1 = readrm16 (rm);

  3247.                 op_grp3_16();

  3248.                 if ( (reg > 1) && (reg < 4) ) {

  3249.                         writerm16 (rm, res16);

  3250.                     }

  3251.                 break;

  3252. 

  3253.             case 0xF8:	/* F8 CLC */

  3254.                 cf = 0;

  3255.                 break;

  3256. 

  3257.             case 0xF9:	/* F9 STC */

  3258.                 cf = 1;

  3259.                 break;

  3260. 

  3261.             case 0xFA:	/* FA CLI */

  3262.                 ifl = 0;

  3263.                 break;

  3264. 

  3265.             case 0xFB:	/* FB STI */

  3266.                 ifl = 1;

  3267.                 break;

  3268. 

  3269.             case 0xFC:	/* FC CLD */

  3270.                 df = 0;

  3271.                 break;

  3272. 

  3273.             case 0xFD:	/* FD STD */

  3274.                 df = 1;

  3275.                 break;

  3276. 

  3277.             case 0xFE:	/* FE GRP4 Eb */

  3278.                 modregrm();

  3279.                 oper1b = readrm8 (rm);

  3280.                 oper2b = 1;

  3281.                 if (!reg) {

  3282.                         tempcf = cf;

  3283.                         res8 = oper1b + oper2b;

  3284.                         flag_add8 (oper1b, oper2b);

  3285.                         cf = tempcf;

  3286.                         writerm8 (rm, res8);

  3287.                     }

  3288.                 else {

  3289.                         tempcf = cf;

  3290.                         res8 = oper1b - oper2b;

  3291.                         flag_sub8 (oper1b, oper2b);

  3292.                         cf = tempcf;

  3293.                         writerm8 (rm, res8);

  3294.                     }

  3295.                 break;

  3296. 

  3297.             case 0xFF:	/* FF GRP5 Ev */

  3298.                 modregrm();

  3299.                 oper1 = readrm16 (rm);

  3300.                 op_grp5();

  3301.                 break;

  3302. 

  3303.             default:

  3304.                 intcall86 (6); /* trip invalid opcode exception (this occurs on the 80186+, 8086/8088 CPUs treat them as NOPs. */

  3305.                                /* technically they aren't exactly like NOPs in most cases, but for our pursoses, that's accurate enough. */

  3306.                 break;

  3307.         }

  3308.     }

  3309.     return 1;

  3310. }

  3311. 

  3312. void reset86(uint16_t startip) {

  3313. 	segregs[regcs] = 0;

  3314. 	ip = startip;

  3315. 	hltstate = 0;

  3316. }