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Mirror of CollapseOS
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collapseos/emul/8086/cpu.c

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  1. /* Extracted from the Fake86 project and heavily modified to run within

  2.    the Collapse OS project with its simple needs.

  3. */

  4. /*

  5.   Fake86: A portable, open-source 8086 PC emulator.

  6.   Copyright (C)2010-2013 Mike Chambers

  7. 

  8.   This program is free software; you can redistribute it and/or

  9.   modify it under the terms of the GNU General Public License

  10.   as published by the Free Software Foundation; either version 2

  11.   of the License, or (at your option) any later version.

  12. 

  13.   This program is distributed in the hope that it will be useful,

  14.   but WITHOUT ANY WARRANTY; without even the implied warranty of

  15.   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

  16.   GNU General Public License for more details.

  17. 

  18.   You should have received a copy of the GNU General Public License

  19.   along with this program; if not, write to the Free Software

  20.   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

  21. */

  22. 

  23. #include <stdint.h>

  24. #include <stdio.h>

  25. #include "cpu.h"

  26. 

  27. #define StepIP(x)	ip += x

  28. #define signext(value)	(int16_t)(int8_t)(value)

  29. #define signext32(value)	(int32_t)(int16_t)(value)

  30. #define getsegreg(regid)	segregs[regid]

  31. #define putsegreg(regid, writeval)	segregs[regid] = writeval

  32. // Warning: those macros below *can't* be called with reg*l and reg*h

  33. #define getreg8(regid)	regs.byteregs[byteregtable[regid]]

  34. #define putreg8(regid, writeval)	regs.byteregs[byteregtable[regid]] = writeval

  35. 

  36. #define makeflagsword() \

  37. 	( \

  38. 	2 | (uint16_t) cf | ((uint16_t) pf << 2) | ((uint16_t) af << 4) | ((uint16_t) zf << 6) | ((uint16_t) sf << 7) | \

  39. 	((uint16_t) tf << 8) | ((uint16_t) ifl << 9) | ((uint16_t) df << 10) | ((uint16_t) of << 11) \

  40. 	)

  41. 

  42. #define decodeflagsword(x) { \

  43. 	temp16 = x; \

  44. 	cf = temp16 & 1; \

  45. 	pf = (temp16 >> 2) & 1; \

  46. 	af = (temp16 >> 4) & 1; \

  47. 	zf = (temp16 >> 6) & 1; \

  48. 	sf = (temp16 >> 7) & 1; \

  49. 	tf = (temp16 >> 8) & 1; \

  50. 	ifl = (temp16 >> 9) & 1; \

  51. 	df = (temp16 >> 10) & 1; \

  52. 	of = (temp16 >> 11) & 1; \

  53. 	}

  54. 

  55. #define modregrm() { \

  56. 	addrbyte = getmem8(segregs[regcs], ip); \

  57. 	StepIP(1); \

  58. 	mode = addrbyte >> 6; \

  59. 	reg = (addrbyte >> 3) & 7; \

  60. 	rm = addrbyte & 7; \

  61. 	switch(mode) \

  62. 	{ \

  63. 	case 0: \

  64. 	if(rm == 6) { \

  65. 	disp16 = getmem16(segregs[regcs], ip); \

  66. 	StepIP(2); \

  67. 	} \

  68. 	if(((rm == 2) || (rm == 3)) && !segoverride) { \

  69. 	useseg = segregs[regss]; \

  70. 	} \

  71. 	break; \

  72.  \

  73. 	case 1: \

  74. 	disp16 = signext(getmem8(segregs[regcs], ip)); \

  75. 	StepIP(1); \

  76. 	if(((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) { \

  77. 	useseg = segregs[regss]; \

  78. 	} \

  79. 	break; \

  80.  \

  81. 	case 2: \

  82. 	disp16 = getmem16(segregs[regcs], ip); \

  83. 	StepIP(2); \

  84. 	if(((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) { \

  85. 	useseg = segregs[regss]; \

  86. 	} \

  87. 	break; \

  88.  \

  89. 	default: \

  90. 	disp8 = 0; \

  91. 	disp16 = 0; \

  92. 	} \

  93. }

  94. uint8_t byteregtable[8] = { regal, regcl, regdl, regbl, regah, regch, regdh, regbh };

  95. 

  96. static const uint8_t parity[0x100] = {

  97. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  98. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  99. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  100. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  101. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  102. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  103. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  104. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1

  105. };

  106. 

  107. uint8_t	RAM[0x100000];

  108. INTHOOK INTHOOKS[0x100] = {0};

  109. uint8_t	opcode, segoverride, reptype, hltstate = 0;

  110. uint16_t segregs[4], savecs, saveip, ip, useseg, oldsp;

  111. uint8_t	tempcf, oldcf, cf, pf, af, zf, sf, tf, ifl, df, of, mode, reg, rm;

  112. uint16_t oper1, oper2, res16, disp16, temp16, dummy, stacksize, frametemp;

  113. uint8_t	oper1b, oper2b, res8, disp8, temp8, nestlev, addrbyte;

  114. uint32_t temp1, temp2, temp3, temp4, temp5, temp32, tempaddr32, ea;

  115. uint64_t totalexec;

  116. 

  117. union _bytewordregs_ regs;

  118. 

  119. uint8_t	portram[0x10000];

  120. 

  121. void intcall86(uint8_t intnum);

  122. 

  123. static void	portout (uint16_t portnum, uint8_t value) {}

  124. static void	portout16 (uint16_t portnum, uint16_t value) {}

  125. static uint8_t	portin (uint16_t portnum) { return 0; }

  126. static uint16_t portin16 (uint16_t portnum) { return 0; }

  127. 

  128. void write86 (uint32_t addr32, uint8_t value) {

  129. 	tempaddr32 = addr32 & 0xFFFFF;

  130.     RAM[tempaddr32] = value;

  131. }

  132. 

  133. void writew86 (uint32_t addr32, uint16_t value) {

  134. 	write86(addr32, (uint8_t) value);

  135. 	write86(addr32 + 1, (uint8_t) (value >> 8) );

  136. }

  137. 

  138. uint8_t read86 (uint32_t addr32) {

  139. 	addr32 &= 0xFFFFF;

  140. 	return (RAM[addr32]);

  141. }

  142. 

  143. uint16_t readw86 (uint32_t addr32) {

  144. 	return ( (uint16_t) read86 (addr32) | (uint16_t) (read86 (addr32 + 1) << 8) );

  145. }

  146. 

  147. static void flag_szp8 (uint8_t value) {

  148. 	if (!value) {

  149. 			zf = 1;

  150. 		}

  151. 	else {

  152. 			zf = 0;	/* set or clear zero flag */

  153. 		}

  154. 

  155. 	if (value & 0x80) {

  156. 			sf = 1;

  157. 		}

  158. 	else {

  159. 			sf = 0;	/* set or clear sign flag */

  160. 		}

  161. 

  162. 	pf = parity[value]; /* retrieve parity state from lookup table */

  163. }

  164. 

  165. static void flag_szp16 (uint16_t value) {

  166. 	if (!value) {

  167. 			zf = 1;

  168. 		}

  169. 	else {

  170. 			zf = 0;	/* set or clear zero flag */

  171. 		}

  172. 

  173. 	if (value & 0x8000) {

  174. 			sf = 1;

  175. 		}

  176. 	else {

  177. 			sf = 0;	/* set or clear sign flag */

  178. 		}

  179. 

  180. 	pf = parity[value & 255];	/* retrieve parity state from lookup table */

  181. }

  182. 

  183. static void flag_log8 (uint8_t value) {

  184. 	flag_szp8 (value);

  185. 	cf = 0;

  186. 	of = 0; /* bitwise logic ops always clear carry and overflow */

  187. }

  188. 

  189. static void flag_log16 (uint16_t value) {

  190. 	flag_szp16 (value);

  191. 	cf = 0;

  192. 	of = 0; /* bitwise logic ops always clear carry and overflow */

  193. }

  194. 

  195. static void flag_adc8 (uint8_t v1, uint8_t v2, uint8_t v3) {

  196. 

  197. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  198. 	uint16_t	dst;

  199. 

  200. 	dst = (uint16_t) v1 + (uint16_t) v2 + (uint16_t) v3;

  201. 	flag_szp8 ( (uint8_t) dst);

  202. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x80) == 0x80) {

  203. 			of = 1;

  204. 		}

  205. 	else {

  206. 			of = 0; /* set or clear overflow flag */

  207. 		}

  208. 

  209. 	if (dst & 0xFF00) {

  210. 			cf = 1;

  211. 		}

  212. 	else {

  213. 			cf = 0; /* set or clear carry flag */

  214. 		}

  215. 

  216. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  217. 			af = 1;

  218. 		}

  219. 	else {

  220. 			af = 0; /* set or clear auxilliary flag */

  221. 		}

  222. }

  223. 

  224. static void flag_adc16 (uint16_t v1, uint16_t v2, uint16_t v3) {

  225. 

  226. 	uint32_t	dst;

  227. 

  228. 	dst = (uint32_t) v1 + (uint32_t) v2 + (uint32_t) v3;

  229. 	flag_szp16 ( (uint16_t) dst);

  230. 	if ( ( ( (dst ^ v1) & (dst ^ v2) ) & 0x8000) == 0x8000) {

  231. 			of = 1;

  232. 		}

  233. 	else {

  234. 			of = 0;

  235. 		}

  236. 

  237. 	if (dst & 0xFFFF0000) {

  238. 			cf = 1;

  239. 		}

  240. 	else {

  241. 			cf = 0;

  242. 		}

  243. 

  244. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  245. 			af = 1;

  246. 		}

  247. 	else {

  248. 			af = 0;

  249. 		}

  250. }

  251. 

  252. static void flag_add8 (uint8_t v1, uint8_t v2) {

  253. 	/* v1 = destination operand, v2 = source operand */

  254. 	uint16_t	dst;

  255. 

  256. 	dst = (uint16_t) v1 + (uint16_t) v2;

  257. 	flag_szp8 ( (uint8_t) dst);

  258. 	if (dst & 0xFF00) {

  259. 			cf = 1;

  260. 		}

  261. 	else {

  262. 			cf = 0;

  263. 		}

  264. 

  265. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x80) == 0x80) {

  266. 			of = 1;

  267. 		}

  268. 	else {

  269. 			of = 0;

  270. 		}

  271. 

  272. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  273. 			af = 1;

  274. 		}

  275. 	else {

  276. 			af = 0;

  277. 		}

  278. }

  279. 

  280. static void flag_add16 (uint16_t v1, uint16_t v2) {

  281. 	/* v1 = destination operand, v2 = source operand */

  282. 	uint32_t	dst;

  283. 

  284. 	dst = (uint32_t) v1 + (uint32_t) v2;

  285. 	flag_szp16 ( (uint16_t) dst);

  286. 	if (dst & 0xFFFF0000) {

  287. 			cf = 1;

  288. 		}

  289. 	else {

  290. 			cf = 0;

  291. 		}

  292. 

  293. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x8000) == 0x8000) {

  294. 			of = 1;

  295. 		}

  296. 	else {

  297. 			of = 0;

  298. 		}

  299. 

  300. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  301. 			af = 1;

  302. 		}

  303. 	else {

  304. 			af = 0;

  305. 		}

  306. }

  307. 

  308. static void flag_sbb8 (uint8_t v1, uint8_t v2, uint8_t v3) {

  309. 

  310. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  311. 	uint16_t	dst;

  312. 

  313. 	v2 += v3;

  314. 	dst = (uint16_t) v1 - (uint16_t) v2;

  315. 	flag_szp8 ( (uint8_t) dst);

  316. 	if (dst & 0xFF00) {

  317. 			cf = 1;

  318. 		}

  319. 	else {

  320. 			cf = 0;

  321. 		}

  322. 

  323. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x80) {

  324. 			of = 1;

  325. 		}

  326. 	else {

  327. 			of = 0;

  328. 		}

  329. 

  330. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  331. 			af = 1;

  332. 		}

  333. 	else {

  334. 			af = 0;

  335. 		}

  336. }

  337. 

  338. static void flag_sbb16 (uint16_t v1, uint16_t v2, uint16_t v3) {

  339. 

  340. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  341. 	uint32_t	dst;

  342. 

  343. 	v2 += v3;

  344. 	dst = (uint32_t) v1 - (uint32_t) v2;

  345. 	flag_szp16 ( (uint16_t) dst);

  346. 	if (dst & 0xFFFF0000) {

  347. 			cf = 1;

  348. 		}

  349. 	else {

  350. 			cf = 0;

  351. 		}

  352. 

  353. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x8000) {

  354. 			of = 1;

  355. 		}

  356. 	else {

  357. 			of = 0;

  358. 		}

  359. 

  360. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  361. 			af = 1;

  362. 		}

  363. 	else {

  364. 			af = 0;

  365. 		}

  366. }

  367. 

  368. static void flag_sub8 (uint8_t v1, uint8_t v2) {

  369. 

  370. 	/* v1 = destination operand, v2 = source operand */

  371. 	uint16_t	dst;

  372. 

  373. 	dst = (uint16_t) v1 - (uint16_t) v2;

  374. 	flag_szp8 ( (uint8_t) dst);

  375. 	if (dst & 0xFF00) {

  376. 			cf = 1;

  377. 		}

  378. 	else {

  379. 			cf = 0;

  380. 		}

  381. 

  382. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x80) {

  383. 			of = 1;

  384. 		}

  385. 	else {

  386. 			of = 0;

  387. 		}

  388. 

  389. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  390. 			af = 1;

  391. 		}

  392. 	else {

  393. 			af = 0;

  394. 		}

  395. }

  396. 

  397. static void flag_sub16 (uint16_t v1, uint16_t v2) {

  398. 

  399. 	/* v1 = destination operand, v2 = source operand */

  400. 	uint32_t	dst;

  401. 

  402. 	dst = (uint32_t) v1 - (uint32_t) v2;

  403. 	flag_szp16 ( (uint16_t) dst);

  404. 	if (dst & 0xFFFF0000) {

  405. 			cf = 1;

  406. 		}

  407. 	else {

  408. 			cf = 0;

  409. 		}

  410. 

  411. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x8000) {

  412. 			of = 1;

  413. 		}

  414. 	else {

  415. 			of = 0;

  416. 		}

  417. 

  418. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  419. 			af = 1;

  420. 		}

  421. 	else {

  422. 			af = 0;

  423. 		}

  424. }

  425. 

  426. static void op_adc8() {

  427. 	res8 = oper1b + oper2b + cf;

  428. 	flag_adc8 (oper1b, oper2b, cf);

  429. }

  430. 

  431. static void op_adc16() {

  432. 	res16 = oper1 + oper2 + cf;

  433. 	flag_adc16 (oper1, oper2, cf);

  434. }

  435. 

  436. static void op_add8() {

  437. 	res8 = oper1b + oper2b;

  438. 	flag_add8 (oper1b, oper2b);

  439. }

  440. 

  441. static void op_add16() {

  442. 	res16 = oper1 + oper2;

  443. 	flag_add16 (oper1, oper2);

  444. }

  445. 

  446. static void op_and8() {

  447. 	res8 = oper1b & oper2b;

  448. 	flag_log8 (res8);

  449. }

  450. 

  451. static void op_and16() {

  452. 	res16 = oper1 & oper2;

  453. 	flag_log16 (res16);

  454. }

  455. 

  456. static void op_or8() {

  457. 	res8 = oper1b | oper2b;

  458. 	flag_log8 (res8);

  459. }

  460. 

  461. static void op_or16() {

  462. 	res16 = oper1 | oper2;

  463. 	flag_log16 (res16);

  464. }

  465. 

  466. static void op_xor8() {

  467. 	res8 = oper1b ^ oper2b;

  468. 	flag_log8 (res8);

  469. }

  470. 

  471. static void op_xor16() {

  472. 	res16 = oper1 ^ oper2;

  473. 	flag_log16 (res16);

  474. }

  475. 

  476. static void op_sub8() {

  477. 	res8 = oper1b - oper2b;

  478. 	flag_sub8 (oper1b, oper2b);

  479. }

  480. 

  481. static void op_sub16() {

  482. 	res16 = oper1 - oper2;

  483. 	flag_sub16 (oper1, oper2);

  484. }

  485. 

  486. static void op_sbb8() {

  487. 	res8 = oper1b - (oper2b + cf);

  488. 	flag_sbb8 (oper1b, oper2b, cf);

  489. }

  490. 

  491. static void op_sbb16() {

  492. 	res16 = oper1 - (oper2 + cf);

  493. 	flag_sbb16 (oper1, oper2, cf);

  494. }

  495. 

  496. static void getea (uint8_t rmval) {

  497. 	uint32_t	tempea;

  498. 

  499. 	tempea = 0;

  500. 	switch (mode) {

  501. 			case 0:

  502. 				switch (rmval) {

  503. 						case 0:

  504. 							tempea = regs.wordregs[regbx] + regs.wordregs[regsi];

  505. 							break;

  506. 						case 1:

  507. 							tempea = regs.wordregs[regbx] + regs.wordregs[regdi];

  508. 							break;

  509. 						case 2:

  510. 							tempea = regs.wordregs[regbp] + regs.wordregs[regsi];

  511. 							break;

  512. 						case 3:

  513. 							tempea = regs.wordregs[regbp] + regs.wordregs[regdi];

  514. 							break;

  515. 						case 4:

  516. 							tempea = regs.wordregs[regsi];

  517. 							break;

  518. 						case 5:

  519. 							tempea = regs.wordregs[regdi];

  520. 							break;

  521. 						case 6:

  522. 							tempea = disp16;

  523. 							break;

  524. 						case 7:

  525. 							tempea = regs.wordregs[regbx];

  526. 							break;

  527. 					}

  528. 				break;

  529. 

  530. 			case 1:

  531. 			case 2:

  532. 				switch (rmval) {

  533. 						case 0:

  534. 							tempea = regs.wordregs[regbx] + regs.wordregs[regsi] + disp16;

  535. 							break;

  536. 						case 1:

  537. 							tempea = regs.wordregs[regbx] + regs.wordregs[regdi] + disp16;

  538. 							break;

  539. 						case 2:

  540. 							tempea = regs.wordregs[regbp] + regs.wordregs[regsi] + disp16;

  541. 							break;

  542. 						case 3:

  543. 							tempea = regs.wordregs[regbp] + regs.wordregs[regdi] + disp16;

  544. 							break;

  545. 						case 4:

  546. 							tempea = regs.wordregs[regsi] + disp16;

  547. 							break;

  548. 						case 5:

  549. 							tempea = regs.wordregs[regdi] + disp16;

  550. 							break;

  551. 						case 6:

  552. 							tempea = regs.wordregs[regbp] + disp16;

  553. 							break;

  554. 						case 7:

  555. 							tempea = regs.wordregs[regbx] + disp16;

  556. 							break;

  557. 					}

  558. 				break;

  559. 		}

  560. 

  561. 	ea = (tempea & 0xFFFF) + (useseg << 4);

  562. }

  563. 

  564. static void push (uint16_t pushval) {

  565. 	regs.wordregs[regsp] = regs.wordregs[regsp] - 2;

  566. 	putmem16 (segregs[regss], regs.wordregs[regsp], pushval);

  567. }

  568. 

  569. static uint16_t pop() {

  570. 

  571. 	uint16_t	tempval;

  572. 

  573. 	tempval = getmem16 (segregs[regss], regs.wordregs[regsp]);

  574. 	regs.wordregs[regsp] = regs.wordregs[regsp] + 2;

  575. 	return tempval;

  576. }

  577. 

  578. static uint16_t readrm16 (uint8_t rmval) {

  579. 	if (mode < 3) {

  580. 			getea (rmval);

  581. 			return read86 (ea) | ( (uint16_t) read86 (ea + 1) << 8);

  582. 		}

  583. 	else {

  584. 			return getreg16 (rmval);

  585. 		}

  586. }

  587. 

  588. static uint8_t readrm8 (uint8_t rmval) {

  589. 	if (mode < 3) {

  590. 			getea (rmval);

  591. 			return read86 (ea);

  592. 		}

  593. 	else {

  594. 			return getreg8 (rmval);

  595. 		}

  596. }

  597. 

  598. static void writerm16 (uint8_t rmval, uint16_t value) {

  599. 	if (mode < 3) {

  600. 			getea (rmval);

  601. 			write86 (ea, value & 0xFF);

  602. 			write86 (ea + 1, value >> 8);

  603. 		}

  604. 	else {

  605. 			putreg16 (rmval, value);

  606. 		}

  607. }

  608. 

  609. static void writerm8 (uint8_t rmval, uint8_t value) {

  610. 	if (mode < 3) {

  611. 			getea (rmval);

  612. 			write86 (ea, value);

  613. 		}

  614. 	else {

  615. 			putreg8 (rmval, value);

  616. 		}

  617. }

  618. 

  619. static uint8_t op_grp2_8 (uint8_t cnt) {

  620. 

  621. 	uint16_t	s;

  622. 	uint16_t	shift;

  623. 	uint16_t	oldcf;

  624. 	uint16_t	msb;

  625. 

  626. 	s = oper1b;

  627. 	oldcf = cf;

  628. 	cnt &= 0x1F;

  629. 	switch (reg) {

  630. 			case 0: /* ROL r/m8 */

  631. 				for (shift = 1; shift <= cnt; shift++) {

  632. 						if (s & 0x80) {

  633. 								cf = 1;

  634. 							}

  635. 						else {

  636. 								cf = 0;

  637. 							}

  638. 

  639. 						s = s << 1;

  640. 						s = s | cf;

  641. 					}

  642. 

  643. 				if (cnt == 1) {

  644. 						//of = cf ^ ( (s >> 7) & 1);

  645. 					if ((s & 0x80) && cf) of = 1; else of = 0;

  646. 					} else of = 0;

  647. 				break;

  648. 

  649. 			case 1: /* ROR r/m8 */

  650. 				for (shift = 1; shift <= cnt; shift++) {

  651. 						cf = s & 1;

  652. 						s = (s >> 1) | (cf << 7);

  653. 					}

  654. 

  655. 				if (cnt == 1) {

  656. 						of = (s >> 7) ^ ( (s >> 6) & 1);

  657. 					}

  658. 				break;

  659. 

  660. 			case 2: /* RCL r/m8 */

  661. 				for (shift = 1; shift <= cnt; shift++) {

  662. 						oldcf = cf;

  663. 						if (s & 0x80) {

  664. 								cf = 1;

  665. 							}

  666. 						else {

  667. 								cf = 0;

  668. 							}

  669. 

  670. 						s = s << 1;

  671. 						s = s | oldcf;

  672. 					}

  673. 

  674. 				if (cnt == 1) {

  675. 						of = cf ^ ( (s >> 7) & 1);

  676. 					}

  677. 				break;

  678. 

  679. 			case 3: /* RCR r/m8 */

  680. 				for (shift = 1; shift <= cnt; shift++) {

  681. 						oldcf = cf;

  682. 						cf = s & 1;

  683. 						s = (s >> 1) | (oldcf << 7);

  684. 					}

  685. 

  686. 				if (cnt == 1) {

  687. 						of = (s >> 7) ^ ( (s >> 6) & 1);

  688. 					}

  689. 				break;

  690. 

  691. 			case 4:

  692. 			case 6: /* SHL r/m8 */

  693. 				for (shift = 1; shift <= cnt; shift++) {

  694. 						if (s & 0x80) {

  695. 								cf = 1;

  696. 							}

  697. 						else {

  698. 								cf = 0;

  699. 							}

  700. 

  701. 						s = (s << 1) & 0xFF;

  702. 					}

  703. 

  704. 				if ( (cnt == 1) && (cf == (s >> 7) ) ) {

  705. 						of = 0;

  706. 					}

  707. 				else {

  708. 						of = 1;

  709. 					}

  710. 

  711. 				flag_szp8 ( (uint8_t) s);

  712. 				break;

  713. 

  714. 			case 5: /* SHR r/m8 */

  715. 				if ( (cnt == 1) && (s & 0x80) ) {

  716. 						of = 1;

  717. 					}

  718. 				else {

  719. 						of = 0;

  720. 					}

  721. 

  722. 				for (shift = 1; shift <= cnt; shift++) {

  723. 						cf = s & 1;

  724. 						s = s >> 1;

  725. 					}

  726. 

  727. 				flag_szp8 ( (uint8_t) s);

  728. 				break;

  729. 

  730. 			case 7: /* SAR r/m8 */

  731. 				for (shift = 1; shift <= cnt; shift++) {

  732. 						msb = s & 0x80;

  733. 						cf = s & 1;

  734. 						s = (s >> 1) | msb;

  735. 					}

  736. 

  737. 				of = 0;

  738. 				flag_szp8 ( (uint8_t) s);

  739. 				break;

  740. 		}

  741. 

  742. 	return s & 0xFF;

  743. }

  744. 

  745. static uint16_t op_grp2_16 (uint8_t cnt) {

  746. 

  747. 	uint32_t	s;

  748. 	uint32_t	shift;

  749. 	uint32_t	oldcf;

  750. 	uint32_t	msb;

  751. 

  752. 	s = oper1;

  753. 	oldcf = cf;

  754. 	cnt &= 0x1F;

  755. 	switch (reg) {

  756. 			case 0: /* ROL r/m8 */

  757. 				for (shift = 1; shift <= cnt; shift++) {

  758. 						if (s & 0x8000) {

  759. 								cf = 1;

  760. 							}

  761. 						else {

  762. 								cf = 0;

  763. 							}

  764. 

  765. 						s = s << 1;

  766. 						s = s | cf;

  767. 					}

  768. 

  769. 				if (cnt == 1) {

  770. 						of = cf ^ ( (s >> 15) & 1);

  771. 					}

  772. 				break;

  773. 

  774. 			case 1: /* ROR r/m8 */

  775. 				for (shift = 1; shift <= cnt; shift++) {

  776. 						cf = s & 1;

  777. 						s = (s >> 1) | (cf << 15);

  778. 					}

  779. 

  780. 				if (cnt == 1) {

  781. 						of = (s >> 15) ^ ( (s >> 14) & 1);

  782. 					}

  783. 				break;

  784. 

  785. 			case 2: /* RCL r/m8 */

  786. 				for (shift = 1; shift <= cnt; shift++) {

  787. 						oldcf = cf;

  788. 						if (s & 0x8000) {

  789. 								cf = 1;

  790. 							}

  791. 						else {

  792. 								cf = 0;

  793. 							}

  794. 

  795. 						s = s << 1;

  796. 						s = s | oldcf;

  797. 					}

  798. 

  799. 				if (cnt == 1) {

  800. 						of = cf ^ ( (s >> 15) & 1);

  801. 					}

  802. 				break;

  803. 

  804. 			case 3: /* RCR r/m8 */

  805. 				for (shift = 1; shift <= cnt; shift++) {

  806. 						oldcf = cf;

  807. 						cf = s & 1;

  808. 						s = (s >> 1) | (oldcf << 15);

  809. 					}

  810. 

  811. 				if (cnt == 1) {

  812. 						of = (s >> 15) ^ ( (s >> 14) & 1);

  813. 					}

  814. 				break;

  815. 

  816. 			case 4:

  817. 			case 6: /* SHL r/m8 */

  818. 				for (shift = 1; shift <= cnt; shift++) {

  819. 						if (s & 0x8000) {

  820. 								cf = 1;

  821. 							}

  822. 						else {

  823. 								cf = 0;

  824. 							}

  825. 

  826. 						s = (s << 1) & 0xFFFF;

  827. 					}

  828. 

  829. 				if ( (cnt == 1) && (cf == (s >> 15) ) ) {

  830. 						of = 0;

  831. 					}

  832. 				else {

  833. 						of = 1;

  834. 					}

  835. 

  836. 				flag_szp16 ( (uint16_t) s);

  837. 				break;

  838. 

  839. 			case 5: /* SHR r/m8 */

  840. 				if ( (cnt == 1) && (s & 0x8000) ) {

  841. 						of = 1;

  842. 					}

  843. 				else {

  844. 						of = 0;

  845. 					}

  846. 

  847. 				for (shift = 1; shift <= cnt; shift++) {

  848. 						cf = s & 1;

  849. 						s = s >> 1;

  850. 					}

  851. 

  852. 				flag_szp16 ( (uint16_t) s);

  853. 				break;

  854. 

  855. 			case 7: /* SAR r/m8 */

  856. 				for (shift = 1; shift <= cnt; shift++) {

  857. 						msb = s & 0x8000;

  858. 						cf = s & 1;

  859. 						s = (s >> 1) | msb;

  860. 					}

  861. 

  862. 				of = 0;

  863. 				flag_szp16 ( (uint16_t) s);

  864. 				break;

  865. 		}

  866. 

  867. 	return (uint16_t) s & 0xFFFF;

  868. }

  869. 

  870. static void op_div8 (uint16_t valdiv, uint8_t divisor) {

  871. 	if (divisor == 0) {

  872. 			intcall86 (0);

  873. 			return;

  874. 		}

  875. 

  876. 	if ( (valdiv / (uint16_t) divisor) > 0xFF) {

  877. 			intcall86 (0);

  878. 			return;

  879. 		}

  880. 

  881. 	regs.byteregs[regah] = valdiv % (uint16_t) divisor;

  882. 	regs.byteregs[regal] = valdiv / (uint16_t) divisor;

  883. }

  884. 

  885. static void op_idiv8 (uint16_t valdiv, uint8_t divisor) {

  886. 

  887. 	uint16_t	s1;

  888. 	uint16_t	s2;

  889. 	uint16_t	d1;

  890. 	uint16_t	d2;

  891. 	int	sign;

  892. 

  893. 	if (divisor == 0) {

  894. 			intcall86 (0);

  895. 			return;

  896. 		}

  897. 

  898. 	s1 = valdiv;

  899. 	s2 = divisor;

  900. 	sign = ( ( (s1 ^ s2) & 0x8000) != 0);

  901. 	s1 = (s1 < 0x8000) ? s1 : ( (~s1 + 1) & 0xffff);

  902. 	s2 = (s2 < 0x8000) ? s2 : ( (~s2 + 1) & 0xffff);

  903. 	d1 = s1 / s2;

  904. 	d2 = s1 % s2;

  905. 	if (d1 & 0xFF00) {

  906. 			intcall86 (0);

  907. 			return;

  908. 		}

  909. 

  910. 	if (sign) {

  911. 			d1 = (~d1 + 1) & 0xff;

  912. 			d2 = (~d2 + 1) & 0xff;

  913. 		}

  914. 

  915. 	regs.byteregs[regah] = (uint8_t) d2;

  916. 	regs.byteregs[regal] = (uint8_t) d1;

  917. }

  918. 

  919. static void op_grp3_8() {

  920. 	oper1 = signext (oper1b);

  921. 	oper2 = signext (oper2b);

  922. 	switch (reg) {

  923. 			case 0:

  924. 			case 1: /* TEST */

  925. 				flag_log8 (oper1b & getmem8 (segregs[regcs], ip) );

  926. 				StepIP (1);

  927. 				break;

  928. 

  929. 			case 2: /* NOT */

  930. 				res8 = ~oper1b;

  931. 				break;

  932. 

  933. 			case 3: /* NEG */

  934. 				res8 = (~oper1b) + 1;

  935. 				flag_sub8 (0, oper1b);

  936. 				if (res8 == 0) {

  937. 						cf = 0;

  938. 					}

  939. 				else {

  940. 						cf = 1;

  941. 					}

  942. 				break;

  943. 

  944. 			case 4: /* MUL */

  945. 				temp1 = (uint32_t) oper1b * (uint32_t) regs.byteregs[regal];

  946. 				regs.wordregs[regax] = temp1 & 0xFFFF;

  947. 				flag_szp8 ( (uint8_t) temp1);

  948. 				if (regs.byteregs[regah]) {

  949. 						cf = 1;

  950. 						of = 1;

  951. 					}

  952. 				else {

  953. 						cf = 0;

  954. 						of = 0;

  955. 					}

  956. 				break;

  957. 

  958. 			case 5: /* IMUL */

  959. 				oper1 = signext (oper1b);

  960. 				temp1 = signext (regs.byteregs[regal]);

  961. 				temp2 = oper1;

  962. 				if ( (temp1 & 0x80) == 0x80) {

  963. 						temp1 = temp1 | 0xFFFFFF00;

  964. 					}

  965. 

  966. 				if ( (temp2 & 0x80) == 0x80) {

  967. 						temp2 = temp2 | 0xFFFFFF00;

  968. 					}

  969. 

  970. 				temp3 = (temp1 * temp2) & 0xFFFF;

  971. 				regs.wordregs[regax] = temp3 & 0xFFFF;

  972. 				if (regs.byteregs[regah]) {

  973. 						cf = 1;

  974. 						of = 1;

  975. 					}

  976. 				else {

  977. 						cf = 0;

  978. 						of = 0;

  979. 					}

  980. 				break;

  981. 

  982. 			case 6: /* DIV */

  983. 				op_div8 (regs.wordregs[regax], oper1b);

  984. 				break;

  985. 

  986. 			case 7: /* IDIV */

  987. 				op_idiv8 (regs.wordregs[regax], oper1b);

  988. 				break;

  989. 		}

  990. }

  991. 

  992. static void op_div16 (uint32_t valdiv, uint16_t divisor) {

  993. 	if (divisor == 0) {

  994. 			intcall86 (0);

  995. 			return;

  996. 		}

  997. 

  998. 	if ( (valdiv / (uint32_t) divisor) > 0xFFFF) {

  999. 			intcall86 (0);

  1000. 			return;

  1001. 		}

  1002. 

  1003. 	regs.wordregs[regdx] = valdiv % (uint32_t) divisor;

  1004. 	regs.wordregs[regax] = valdiv / (uint32_t) divisor;

  1005. }

  1006. 

  1007. static void op_idiv16 (uint32_t valdiv, uint16_t divisor) {

  1008. 

  1009. 	uint32_t	d1;

  1010. 	uint32_t	d2;

  1011. 	uint32_t	s1;

  1012. 	uint32_t	s2;

  1013. 	int	sign;

  1014. 

  1015. 	if (divisor == 0) {

  1016. 			intcall86 (0);

  1017. 			return;

  1018. 		}

  1019. 

  1020. 	s1 = valdiv;

  1021. 	s2 = divisor;

  1022. 	s2 = (s2 & 0x8000) ? (s2 | 0xffff0000) : s2;

  1023. 	sign = ( ( (s1 ^ s2) & 0x80000000) != 0);

  1024. 	s1 = (s1 < 0x80000000) ? s1 : ( (~s1 + 1) & 0xffffffff);

  1025. 	s2 = (s2 < 0x80000000) ? s2 : ( (~s2 + 1) & 0xffffffff);

  1026. 	d1 = s1 / s2;

  1027. 	d2 = s1 % s2;

  1028. 	if (d1 & 0xFFFF0000) {

  1029. 			intcall86 (0);

  1030. 			return;

  1031. 		}

  1032. 

  1033. 	if (sign) {

  1034. 			d1 = (~d1 + 1) & 0xffff;

  1035. 			d2 = (~d2 + 1) & 0xffff;

  1036. 		}

  1037. 

  1038. 	regs.wordregs[regax] = d1;

  1039. 	regs.wordregs[regdx] = d2;

  1040. }

  1041. 

  1042. static void op_grp3_16() {

  1043. 	switch (reg) {

  1044. 			case 0:

  1045. 			case 1: /* TEST */

  1046. 				flag_log16 (oper1 & getmem16 (segregs[regcs], ip) );

  1047. 				StepIP (2);

  1048. 				break;

  1049. 

  1050. 			case 2: /* NOT */

  1051. 				res16 = ~oper1;

  1052. 				break;

  1053. 

  1054. 			case 3: /* NEG */

  1055. 				res16 = (~oper1) + 1;

  1056. 				flag_sub16 (0, oper1);

  1057. 				if (res16) {

  1058. 						cf = 1;

  1059. 					}

  1060. 				else {

  1061. 						cf = 0;

  1062. 					}

  1063. 				break;

  1064. 

  1065. 			case 4: /* MUL */

  1066. 				temp1 = (uint32_t) oper1 * (uint32_t) regs.wordregs[regax];

  1067. 				regs.wordregs[regax] = temp1 & 0xFFFF;

  1068. 				regs.wordregs[regdx] = temp1 >> 16;

  1069. 				flag_szp16 ( (uint16_t) temp1);

  1070. 				if (regs.wordregs[regdx]) {

  1071. 						cf = 1;

  1072. 						of = 1;

  1073. 					}

  1074. 				else {

  1075. 						cf = 0;

  1076. 						of = 0;

  1077. 					}

  1078. 				break;

  1079. 

  1080. 			case 5: /* IMUL */

  1081. 				temp1 = regs.wordregs[regax];

  1082. 				temp2 = oper1;

  1083. 				if (temp1 & 0x8000) {

  1084. 						temp1 |= 0xFFFF0000;

  1085. 					}

  1086. 

  1087. 				if (temp2 & 0x8000) {

  1088. 						temp2 |= 0xFFFF0000;

  1089. 					}

  1090. 

  1091. 				temp3 = temp1 * temp2;

  1092. 				regs.wordregs[regax] = temp3 & 0xFFFF;	/* into register ax */

  1093. 				regs.wordregs[regdx] = temp3 >> 16;	/* into register dx */

  1094. 				if (regs.wordregs[regdx]) {

  1095. 						cf = 1;

  1096. 						of = 1;

  1097. 					}

  1098. 				else {

  1099. 						cf = 0;

  1100. 						of = 0;

  1101. 					}

  1102. 				break;

  1103. 

  1104. 			case 6: /* DIV */

  1105. 				op_div16 ( ( (uint32_t) regs.wordregs[regdx] << 16) + regs.wordregs[regax], oper1);

  1106. 				break;

  1107. 

  1108. 			case 7: /* DIV */

  1109. 				op_idiv16 ( ( (uint32_t) regs.wordregs[regdx] << 16) + regs.wordregs[regax], oper1);

  1110. 				break;

  1111. 		}

  1112. }

  1113. 

  1114. static void op_grp5() {

  1115. 	switch (reg) {

  1116. 			case 0: /* INC Ev */

  1117. 				oper2 = 1;

  1118. 				tempcf = cf;

  1119. 				op_add16();

  1120. 				cf = tempcf;

  1121. 				writerm16 (rm, res16);

  1122. 				break;

  1123. 

  1124. 			case 1: /* DEC Ev */

  1125. 				oper2 = 1;

  1126. 				tempcf = cf;

  1127. 				op_sub16();

  1128. 				cf = tempcf;

  1129. 				writerm16 (rm, res16);

  1130. 				break;

  1131. 

  1132. 			case 2: /* CALL Ev */

  1133. 				push (ip);

  1134. 				ip = oper1;

  1135. 				break;

  1136. 

  1137. 			case 3: /* CALL Mp */

  1138. 				push (segregs[regcs]);

  1139. 				push (ip);

  1140. 				getea (rm);

  1141. 				ip = (uint16_t) read86 (ea) + (uint16_t) read86 (ea + 1) * 256;

  1142. 				segregs[regcs] = (uint16_t) read86 (ea + 2) + (uint16_t) read86 (ea + 3) * 256;

  1143. 				break;

  1144. 

  1145. 			case 4: /* JMP Ev */

  1146. 				ip = oper1;

  1147. 				break;

  1148. 

  1149. 			case 5: /* JMP Mp */

  1150. 				getea (rm);

  1151. 				ip = (uint16_t) read86 (ea) + (uint16_t) read86 (ea + 1) * 256;

  1152. 				segregs[regcs] = (uint16_t) read86 (ea + 2) + (uint16_t) read86 (ea + 3) * 256;

  1153. 				break;

  1154. 

  1155. 			case 6: /* PUSH Ev */

  1156. 				push (oper1);

  1157. 				break;

  1158. 		}

  1159. }

  1160. 

  1161. void intcall86(uint8_t intnum) {

  1162.     if (intnum == 0) {

  1163.         fprintf(stderr, "INT 0 called, halting\n");

  1164.         hltstate = 1;

  1165.         return;

  1166.     }

  1167.     if (INTHOOKS[intnum] != NULL) {

  1168.         INTHOOKS[intnum]();

  1169.         return;

  1170.     }

  1171.     fprintf(stderr, "Unknown INT called: %x\n", intnum);

  1172. 	/*push (makeflagsword() );

  1173. 	push (segregs[regcs]);

  1174. 	push (ip);

  1175. 	segregs[regcs] = getmem16 (0, (uint16_t) intnum * 4 + 2);

  1176. 	ip = getmem16 (0, (uint16_t) intnum * 4);

  1177. 	ifl = 0;

  1178. 	tf = 0;*/

  1179. }

  1180. 

  1181. int exec86(int execloops) {

  1182. 	int loopcount;

  1183. 	uint8_t docontinue;

  1184. 	static uint16_t firstip;

  1185. 

  1186. 	for (loopcount = 0; loopcount < execloops; loopcount++) {

  1187.         if (hltstate) return 0;

  1188. 

  1189.         reptype = 0;

  1190.         segoverride = 0;

  1191.         useseg = segregs[regds];

  1192.         docontinue = 0;

  1193.         firstip = ip;

  1194. 

  1195.         while (!docontinue) {

  1196.             segregs[regcs] = segregs[regcs] & 0xFFFF;

  1197.             ip = ip & 0xFFFF;

  1198.             savecs = segregs[regcs];

  1199.             saveip = ip;

  1200.             opcode = getmem8 (segregs[regcs], ip);

  1201.             StepIP (1);

  1202. 

  1203.             switch (opcode) {

  1204.                         /* segment prefix check */

  1205.                     case 0x2E:	/* segment segregs[regcs] */

  1206.                         useseg = segregs[regcs];

  1207.                         segoverride = 1;

  1208.                         break;

  1209. 

  1210.                     case 0x3E:	/* segment segregs[regds] */

  1211.                         useseg = segregs[regds];

  1212.                         segoverride = 1;

  1213.                         break;

  1214. 

  1215.                     case 0x26:	/* segment segregs[reges] */

  1216.                         useseg = segregs[reges];

  1217.                         segoverride = 1;

  1218.                         break;

  1219. 

  1220.                     case 0x36:	/* segment segregs[regss] */

  1221.                         useseg = segregs[regss];

  1222.                         segoverride = 1;

  1223.                         break;

  1224. 

  1225.                         /* repetition prefix check */

  1226.                     case 0xF3:	/* REP/REPE/REPZ */

  1227.                         reptype = 1;

  1228.                         break;

  1229. 

  1230.                     case 0xF2:	/* REPNE/REPNZ */

  1231.                         reptype = 2;

  1232.                         break;

  1233. 

  1234.                     default:

  1235.                         docontinue = 1;

  1236.                         break;

  1237.                 }

  1238.         }

  1239. 

  1240.         totalexec++;

  1241. 

  1242.         switch (opcode) {

  1243.             case 0x0:	/* 00 ADD Eb Gb */

  1244.                 modregrm();

  1245.                 oper1b = readrm8 (rm);

  1246.                 oper2b = getreg8 (reg);

  1247.                 op_add8();

  1248.                 writerm8 (rm, res8);

  1249.                 break;

  1250. 

  1251.             case 0x1:	/* 01 ADD Ev Gv */

  1252.                 modregrm();

  1253.                 oper1 = readrm16 (rm);

  1254.                 oper2 = getreg16 (reg);

  1255.                 op_add16();

  1256.                 writerm16 (rm, res16);

  1257.                 break;

  1258. 

  1259.             case 0x2:	/* 02 ADD Gb Eb */

  1260.                 modregrm();

  1261.                 oper1b = getreg8 (reg);

  1262.                 oper2b = readrm8 (rm);

  1263.                 op_add8();

  1264.                 putreg8 (reg, res8);

  1265.                 break;

  1266. 

  1267.             case 0x3:	/* 03 ADD Gv Ev */

  1268.                 modregrm();

  1269.                 oper1 = getreg16 (reg);

  1270.                 oper2 = readrm16 (rm);

  1271.                 op_add16();

  1272.                 putreg16 (reg, res16);

  1273.                 break;

  1274. 

  1275.             case 0x4:	/* 04 ADD regs.byteregs[regal] Ib */

  1276.                 oper1b = regs.byteregs[regal];

  1277.                 oper2b = getmem8 (segregs[regcs], ip);

  1278.                 StepIP (1);

  1279.                 op_add8();

  1280.                 regs.byteregs[regal] = res8;

  1281.                 break;

  1282. 

  1283.             case 0x5:	/* 05 ADD eAX Iv */

  1284.                 oper1 = regs.wordregs[regax];

  1285.                 oper2 = getmem16 (segregs[regcs], ip);

  1286.                 StepIP (2);

  1287.                 op_add16();

  1288.                 regs.wordregs[regax] = res16;

  1289.                 break;

  1290. 

  1291.             case 0x6:	/* 06 PUSH segregs[reges] */

  1292.                 push (segregs[reges]);

  1293.                 break;

  1294. 

  1295.             case 0x7:	/* 07 POP segregs[reges] */

  1296.                 segregs[reges] = pop();

  1297.                 break;

  1298. 

  1299.             case 0x8:	/* 08 OR Eb Gb */

  1300.                 modregrm();

  1301.                 oper1b = readrm8 (rm);

  1302.                 oper2b = getreg8 (reg);

  1303.                 op_or8();

  1304.                 writerm8 (rm, res8);

  1305.                 break;

  1306. 

  1307.             case 0x9:	/* 09 OR Ev Gv */

  1308.                 modregrm();

  1309.                 oper1 = readrm16 (rm);

  1310.                 oper2 = getreg16 (reg);

  1311.                 op_or16();

  1312.                 writerm16 (rm, res16);

  1313.                 break;

  1314. 

  1315.             case 0xA:	/* 0A OR Gb Eb */

  1316.                 modregrm();

  1317.                 oper1b = getreg8 (reg);

  1318.                 oper2b = readrm8 (rm);

  1319.                 op_or8();

  1320.                 putreg8 (reg, res8);

  1321.                 break;

  1322. 

  1323.             case 0xB:	/* 0B OR Gv Ev */

  1324.                 modregrm();

  1325.                 oper1 = getreg16 (reg);

  1326.                 oper2 = readrm16 (rm);

  1327.                 op_or16();

  1328.                 putreg16 (reg, res16);

  1329.                 break;

  1330. 

  1331.             case 0xC:	/* 0C OR regs.byteregs[regal] Ib */

  1332.                 oper1b = regs.byteregs[regal];

  1333.                 oper2b = getmem8 (segregs[regcs], ip);

  1334.                 StepIP (1);

  1335.                 op_or8();

  1336.                 regs.byteregs[regal] = res8;

  1337.                 break;

  1338. 

  1339.             case 0xD:	/* 0D OR eAX Iv */

  1340.                 oper1 = regs.wordregs[regax];

  1341.                 oper2 = getmem16 (segregs[regcs], ip);

  1342.                 StepIP (2);

  1343.                 op_or16();

  1344.                 regs.wordregs[regax] = res16;

  1345.                 break;

  1346. 

  1347.             case 0xE:	/* 0E PUSH segregs[regcs] */

  1348.                 push (segregs[regcs]);

  1349.                 break;

  1350. 

  1351.             case 0x10:	/* 10 ADC Eb Gb */

  1352.                 modregrm();

  1353.                 oper1b = readrm8 (rm);

  1354.                 oper2b = getreg8 (reg);

  1355.                 op_adc8();

  1356.                 writerm8 (rm, res8);

  1357.                 break;

  1358. 

  1359.             case 0x11:	/* 11 ADC Ev Gv */

  1360.                 modregrm();

  1361.                 oper1 = readrm16 (rm);

  1362.                 oper2 = getreg16 (reg);

  1363.                 op_adc16();

  1364.                 writerm16 (rm, res16);

  1365.                 break;

  1366. 

  1367.             case 0x12:	/* 12 ADC Gb Eb */

  1368.                 modregrm();

  1369.                 oper1b = getreg8 (reg);

  1370.                 oper2b = readrm8 (rm);

  1371.                 op_adc8();

  1372.                 putreg8 (reg, res8);

  1373.                 break;

  1374. 

  1375.             case 0x13:	/* 13 ADC Gv Ev */

  1376.                 modregrm();

  1377.                 oper1 = getreg16 (reg);

  1378.                 oper2 = readrm16 (rm);

  1379.                 op_adc16();

  1380.                 putreg16 (reg, res16);

  1381.                 break;

  1382. 

  1383.             case 0x14:	/* 14 ADC regs.byteregs[regal] Ib */

  1384.                 oper1b = regs.byteregs[regal];

  1385.                 oper2b = getmem8 (segregs[regcs], ip);

  1386.                 StepIP (1);

  1387.                 op_adc8();

  1388.                 regs.byteregs[regal] = res8;

  1389.                 break;

  1390. 

  1391.             case 0x15:	/* 15 ADC eAX Iv */

  1392.                 oper1 = regs.wordregs[regax];

  1393.                 oper2 = getmem16 (segregs[regcs], ip);

  1394.                 StepIP (2);

  1395.                 op_adc16();

  1396.                 regs.wordregs[regax] = res16;

  1397.                 break;

  1398. 

  1399.             case 0x16:	/* 16 PUSH segregs[regss] */

  1400.                 push (segregs[regss]);

  1401.                 break;

  1402. 

  1403.             case 0x17:	/* 17 POP segregs[regss] */

  1404.                 segregs[regss] = pop();

  1405.                 break;

  1406. 

  1407.             case 0x18:	/* 18 SBB Eb Gb */

  1408.                 modregrm();

  1409.                 oper1b = readrm8 (rm);

  1410.                 oper2b = getreg8 (reg);

  1411.                 op_sbb8();

  1412.                 writerm8 (rm, res8);

  1413.                 break;

  1414. 

  1415.             case 0x19:	/* 19 SBB Ev Gv */

  1416.                 modregrm();

  1417.                 oper1 = readrm16 (rm);

  1418.                 oper2 = getreg16 (reg);

  1419.                 op_sbb16();

  1420.                 writerm16 (rm, res16);

  1421.                 break;

  1422. 

  1423.             case 0x1A:	/* 1A SBB Gb Eb */

  1424.                 modregrm();

  1425.                 oper1b = getreg8 (reg);

  1426.                 oper2b = readrm8 (rm);

  1427.                 op_sbb8();

  1428.                 putreg8 (reg, res8);

  1429.                 break;

  1430. 

  1431.             case 0x1B:	/* 1B SBB Gv Ev */

  1432.                 modregrm();

  1433.                 oper1 = getreg16 (reg);

  1434.                 oper2 = readrm16 (rm);

  1435.                 op_sbb16();

  1436.                 putreg16 (reg, res16);

  1437.                 break;

  1438. 

  1439.             case 0x1C:	/* 1C SBB regs.byteregs[regal] Ib */

  1440.                 oper1b = regs.byteregs[regal];

  1441.                 oper2b = getmem8 (segregs[regcs], ip);

  1442.                 StepIP (1);

  1443.                 op_sbb8();

  1444.                 regs.byteregs[regal] = res8;

  1445.                 break;

  1446. 

  1447.             case 0x1D:	/* 1D SBB eAX Iv */

  1448.                 oper1 = regs.wordregs[regax];

  1449.                 oper2 = getmem16 (segregs[regcs], ip);

  1450.                 StepIP (2);

  1451.                 op_sbb16();

  1452.                 regs.wordregs[regax] = res16;

  1453.                 break;

  1454. 

  1455.             case 0x1E:	/* 1E PUSH segregs[regds] */

  1456.                 push (segregs[regds]);

  1457.                 break;

  1458. 

  1459.             case 0x1F:	/* 1F POP segregs[regds] */

  1460.                 segregs[regds] = pop();

  1461.                 break;

  1462. 

  1463.             case 0x20:	/* 20 AND Eb Gb */

  1464.                 modregrm();

  1465.                 oper1b = readrm8 (rm);

  1466.                 oper2b = getreg8 (reg);

  1467.                 op_and8();

  1468.                 writerm8 (rm, res8);

  1469.                 break;

  1470. 

  1471.             case 0x21:	/* 21 AND Ev Gv */

  1472.                 modregrm();

  1473.                 oper1 = readrm16 (rm);

  1474.                 oper2 = getreg16 (reg);

  1475.                 op_and16();

  1476.                 writerm16 (rm, res16);

  1477.                 break;

  1478. 

  1479.             case 0x22:	/* 22 AND Gb Eb */

  1480.                 modregrm();

  1481.                 oper1b = getreg8 (reg);

  1482.                 oper2b = readrm8 (rm);

  1483.                 op_and8();

  1484.                 putreg8 (reg, res8);

  1485.                 break;

  1486. 

  1487.             case 0x23:	/* 23 AND Gv Ev */

  1488.                 modregrm();

  1489.                 oper1 = getreg16 (reg);

  1490.                 oper2 = readrm16 (rm);

  1491.                 op_and16();

  1492.                 putreg16 (reg, res16);

  1493.                 break;

  1494. 

  1495.             case 0x24:	/* 24 AND regs.byteregs[regal] Ib */

  1496.                 oper1b = regs.byteregs[regal];

  1497.                 oper2b = getmem8 (segregs[regcs], ip);

  1498.                 StepIP (1);

  1499.                 op_and8();

  1500.                 regs.byteregs[regal] = res8;

  1501.                 break;

  1502. 

  1503.             case 0x25:	/* 25 AND eAX Iv */

  1504.                 oper1 = regs.wordregs[regax];

  1505.                 oper2 = getmem16 (segregs[regcs], ip);

  1506.                 StepIP (2);

  1507.                 op_and16();

  1508.                 regs.wordregs[regax] = res16;

  1509.                 break;

  1510. 

  1511.             case 0x27:	/* 27 DAA */

  1512.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1513.                         oper1 = regs.byteregs[regal] + 6;

  1514.                         regs.byteregs[regal] = oper1 & 255;

  1515.                         if (oper1 & 0xFF00) {

  1516.                                 cf = 1;

  1517.                             }

  1518.                         else {

  1519.                                 cf = 0;

  1520.                             }

  1521. 

  1522.                         af = 1;

  1523.                     }

  1524.                 else {

  1525.                         //af = 0;

  1526.                     }

  1527. 

  1528.                 if ( (regs.byteregs[regal]  > 0x9F) || (cf == 1) ) {

  1529.                         regs.byteregs[regal] = regs.byteregs[regal] + 0x60;

  1530.                         cf = 1;

  1531.                     }

  1532.                 else {

  1533.                         //cf = 0;

  1534.                     }

  1535. 

  1536.                 regs.byteregs[regal] = regs.byteregs[regal] & 255;

  1537.                 flag_szp8 (regs.byteregs[regal]);

  1538.                 break;

  1539. 

  1540.             case 0x28:	/* 28 SUB Eb Gb */

  1541.                 modregrm();

  1542.                 oper1b = readrm8 (rm);

  1543.                 oper2b = getreg8 (reg);

  1544.                 op_sub8();

  1545.                 writerm8 (rm, res8);

  1546.                 break;

  1547. 

  1548.             case 0x29:	/* 29 SUB Ev Gv */

  1549.                 modregrm();

  1550.                 oper1 = readrm16 (rm);

  1551.                 oper2 = getreg16 (reg);

  1552.                 op_sub16();

  1553.                 writerm16 (rm, res16);

  1554.                 break;

  1555. 

  1556.             case 0x2A:	/* 2A SUB Gb Eb */

  1557.                 modregrm();

  1558.                 oper1b = getreg8 (reg);

  1559.                 oper2b = readrm8 (rm);

  1560.                 op_sub8();

  1561.                 putreg8 (reg, res8);

  1562.                 break;

  1563. 

  1564.             case 0x2B:	/* 2B SUB Gv Ev */

  1565.                 modregrm();

  1566.                 oper1 = getreg16 (reg);

  1567.                 oper2 = readrm16 (rm);

  1568.                 op_sub16();

  1569.                 putreg16 (reg, res16);

  1570.                 break;

  1571. 

  1572.             case 0x2C:	/* 2C SUB regs.byteregs[regal] Ib */

  1573.                 oper1b = regs.byteregs[regal];

  1574.                 oper2b = getmem8 (segregs[regcs], ip);

  1575.                 StepIP (1);

  1576.                 op_sub8();

  1577.                 regs.byteregs[regal] = res8;

  1578.                 break;

  1579. 

  1580.             case 0x2D:	/* 2D SUB eAX Iv */

  1581.                 oper1 = regs.wordregs[regax];

  1582.                 oper2 = getmem16 (segregs[regcs], ip);

  1583.                 StepIP (2);

  1584.                 op_sub16();

  1585.                 regs.wordregs[regax] = res16;

  1586.                 break;

  1587. 

  1588.             case 0x2F:	/* 2F DAS */

  1589.                 if ( ( (regs.byteregs[regal] & 15) > 9) || (af == 1) ) {

  1590.                         oper1 = regs.byteregs[regal] - 6;

  1591.                         regs.byteregs[regal] = oper1 & 255;

  1592.                         if (oper1 & 0xFF00) {

  1593.                                 cf = 1;

  1594.                             }

  1595.                         else {

  1596.                                 cf = 0;

  1597.                             }

  1598. 

  1599.                         af = 1;

  1600.                     }

  1601.                 else {

  1602.                         af = 0;

  1603.                     }

  1604. 

  1605.                 if ( ( (regs.byteregs[regal] & 0xF0) > 0x90) || (cf == 1) ) {

  1606.                         regs.byteregs[regal] = regs.byteregs[regal] - 0x60;

  1607.                         cf = 1;

  1608.                     }

  1609.                 else {

  1610.                         cf = 0;

  1611.                     }

  1612. 

  1613.                 flag_szp8 (regs.byteregs[regal]);

  1614.                 break;

  1615. 

  1616.             case 0x30:	/* 30 XOR Eb Gb */

  1617.                 modregrm();

  1618.                 oper1b = readrm8 (rm);

  1619.                 oper2b = getreg8 (reg);

  1620.                 op_xor8();

  1621.                 writerm8 (rm, res8);

  1622.                 break;

  1623. 

  1624.             case 0x31:	/* 31 XOR Ev Gv */

  1625.                 modregrm();

  1626.                 oper1 = readrm16 (rm);

  1627.                 oper2 = getreg16 (reg);

  1628.                 op_xor16();

  1629.                 writerm16 (rm, res16);

  1630.                 break;

  1631. 

  1632.             case 0x32:	/* 32 XOR Gb Eb */

  1633.                 modregrm();

  1634.                 oper1b = getreg8 (reg);

  1635.                 oper2b = readrm8 (rm);

  1636.                 op_xor8();

  1637.                 putreg8 (reg, res8);

  1638.                 break;

  1639. 

  1640.             case 0x33:	/* 33 XOR Gv Ev */

  1641.                 modregrm();

  1642.                 oper1 = getreg16 (reg);

  1643.                 oper2 = readrm16 (rm);

  1644.                 op_xor16();

  1645.                 putreg16 (reg, res16);

  1646.                 break;

  1647. 

  1648.             case 0x34:	/* 34 XOR regs.byteregs[regal] Ib */

  1649.                 oper1b = regs.byteregs[regal];

  1650.                 oper2b = getmem8 (segregs[regcs], ip);

  1651.                 StepIP (1);

  1652.                 op_xor8();

  1653.                 regs.byteregs[regal] = res8;

  1654.                 break;

  1655. 

  1656.             case 0x35:	/* 35 XOR eAX Iv */

  1657.                 oper1 = regs.wordregs[regax];

  1658.                 oper2 = getmem16 (segregs[regcs], ip);

  1659.                 StepIP (2);

  1660.                 op_xor16();

  1661.                 regs.wordregs[regax] = res16;

  1662.                 break;

  1663. 

  1664.             case 0x37:	/* 37 AAA ASCII */

  1665.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1666.                         regs.byteregs[regal] = regs.byteregs[regal] + 6;

  1667.                         regs.byteregs[regah] = regs.byteregs[regah] + 1;

  1668.                         af = 1;

  1669.                         cf = 1;

  1670.                     }

  1671.                 else {

  1672.                         af = 0;

  1673.                         cf = 0;

  1674.                     }

  1675. 

  1676.                 regs.byteregs[regal] = regs.byteregs[regal] & 0xF;

  1677.                 break;

  1678. 

  1679.             case 0x38:	/* 38 CMP Eb Gb */

  1680.                 modregrm();

  1681.                 oper1b = readrm8 (rm);

  1682.                 oper2b = getreg8 (reg);

  1683.                 flag_sub8 (oper1b, oper2b);

  1684.                 break;

  1685. 

  1686.             case 0x39:	/* 39 CMP Ev Gv */

  1687.                 modregrm();

  1688.                 oper1 = readrm16 (rm);

  1689.                 oper2 = getreg16 (reg);

  1690.                 flag_sub16 (oper1, oper2);

  1691.                 break;

  1692. 

  1693.             case 0x3A:	/* 3A CMP Gb Eb */

  1694.                 modregrm();

  1695.                 oper1b = getreg8 (reg);

  1696.                 oper2b = readrm8 (rm);

  1697.                 flag_sub8 (oper1b, oper2b);

  1698.                 break;

  1699. 

  1700.             case 0x3B:	/* 3B CMP Gv Ev */

  1701.                 modregrm();

  1702.                 oper1 = getreg16 (reg);

  1703.                 oper2 = readrm16 (rm);

  1704.                 flag_sub16 (oper1, oper2);

  1705.                 break;

  1706. 

  1707.             case 0x3C:	/* 3C CMP regs.byteregs[regal] Ib */

  1708.                 oper1b = regs.byteregs[regal];

  1709.                 oper2b = getmem8 (segregs[regcs], ip);

  1710.                 StepIP (1);

  1711.                 flag_sub8 (oper1b, oper2b);

  1712.                 break;

  1713. 

  1714.             case 0x3D:	/* 3D CMP eAX Iv */

  1715.                 oper1 = regs.wordregs[regax];

  1716.                 oper2 = getmem16 (segregs[regcs], ip);

  1717.                 StepIP (2);

  1718.                 flag_sub16 (oper1, oper2);

  1719.                 break;

  1720. 

  1721.             case 0x3F:	/* 3F AAS ASCII */

  1722.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1723.                         regs.byteregs[regal] = regs.byteregs[regal] - 6;

  1724.                         regs.byteregs[regah] = regs.byteregs[regah] - 1;

  1725.                         af = 1;

  1726.                         cf = 1;

  1727.                     }

  1728.                 else {

  1729.                         af = 0;

  1730.                         cf = 0;

  1731.                     }

  1732. 

  1733.                 regs.byteregs[regal] = regs.byteregs[regal] & 0xF;

  1734.                 break;

  1735. 

  1736.             case 0x40:	/* 40 INC eAX */

  1737.                 oldcf = cf;

  1738.                 oper1 = regs.wordregs[regax];

  1739.                 oper2 = 1;

  1740.                 op_add16();

  1741.                 cf = oldcf;

  1742.                 regs.wordregs[regax] = res16;

  1743.                 break;

  1744. 

  1745.             case 0x41:	/* 41 INC eCX */

  1746.                 oldcf = cf;

  1747.                 oper1 = regs.wordregs[regcx];

  1748.                 oper2 = 1;

  1749.                 op_add16();

  1750.                 cf = oldcf;

  1751.                 regs.wordregs[regcx] = res16;

  1752.                 break;

  1753. 

  1754.             case 0x42:	/* 42 INC eDX */

  1755.                 oldcf = cf;

  1756.                 oper1 = regs.wordregs[regdx];

  1757.                 oper2 = 1;

  1758.                 op_add16();

  1759.                 cf = oldcf;

  1760.                 regs.wordregs[regdx] = res16;

  1761.                 break;

  1762. 

  1763.             case 0x43:	/* 43 INC eBX */

  1764.                 oldcf = cf;

  1765.                 oper1 = regs.wordregs[regbx];

  1766.                 oper2 = 1;

  1767.                 op_add16();

  1768.                 cf = oldcf;

  1769.                 regs.wordregs[regbx] = res16;

  1770.                 break;

  1771. 

  1772.             case 0x44:	/* 44 INC eSP */

  1773.                 oldcf = cf;

  1774.                 oper1 = regs.wordregs[regsp];

  1775.                 oper2 = 1;

  1776.                 op_add16();

  1777.                 cf = oldcf;

  1778.                 regs.wordregs[regsp] = res16;

  1779.                 break;

  1780. 

  1781.             case 0x45:	/* 45 INC eBP */

  1782.                 oldcf = cf;

  1783.                 oper1 = regs.wordregs[regbp];

  1784.                 oper2 = 1;

  1785.                 op_add16();

  1786.                 cf = oldcf;

  1787.                 regs.wordregs[regbp] = res16;

  1788.                 break;

  1789. 

  1790.             case 0x46:	/* 46 INC eSI */

  1791.                 oldcf = cf;

  1792.                 oper1 = regs.wordregs[regsi];

  1793.                 oper2 = 1;

  1794.                 op_add16();

  1795.                 cf = oldcf;

  1796.                 regs.wordregs[regsi] = res16;

  1797.                 break;

  1798. 

  1799.             case 0x47:	/* 47 INC eDI */

  1800.                 oldcf = cf;

  1801.                 oper1 = regs.wordregs[regdi];

  1802.                 oper2 = 1;

  1803.                 op_add16();

  1804.                 cf = oldcf;

  1805.                 regs.wordregs[regdi] = res16;

  1806.                 break;

  1807. 

  1808.             case 0x48:	/* 48 DEC eAX */

  1809.                 oldcf = cf;

  1810.                 oper1 = regs.wordregs[regax];

  1811.                 oper2 = 1;

  1812.                 op_sub16();

  1813.                 cf = oldcf;

  1814.                 regs.wordregs[regax] = res16;

  1815.                 break;

  1816. 

  1817.             case 0x49:	/* 49 DEC eCX */

  1818.                 oldcf = cf;

  1819.                 oper1 = regs.wordregs[regcx];

  1820.                 oper2 = 1;

  1821.                 op_sub16();

  1822.                 cf = oldcf;

  1823.                 regs.wordregs[regcx] = res16;

  1824.                 break;

  1825. 

  1826.             case 0x4A:	/* 4A DEC eDX */

  1827.                 oldcf = cf;

  1828.                 oper1 = regs.wordregs[regdx];

  1829.                 oper2 = 1;

  1830.                 op_sub16();

  1831.                 cf = oldcf;

  1832.                 regs.wordregs[regdx] = res16;

  1833.                 break;

  1834. 

  1835.             case 0x4B:	/* 4B DEC eBX */

  1836.                 oldcf = cf;

  1837.                 oper1 = regs.wordregs[regbx];

  1838.                 oper2 = 1;

  1839.                 op_sub16();

  1840.                 cf = oldcf;

  1841.                 regs.wordregs[regbx] = res16;

  1842.                 break;

  1843. 

  1844.             case 0x4C:	/* 4C DEC eSP */

  1845.                 oldcf = cf;

  1846.                 oper1 = regs.wordregs[regsp];

  1847.                 oper2 = 1;

  1848.                 op_sub16();

  1849.                 cf = oldcf;

  1850.                 regs.wordregs[regsp] = res16;

  1851.                 break;

  1852. 

  1853.             case 0x4D:	/* 4D DEC eBP */

  1854.                 oldcf = cf;

  1855.                 oper1 = regs.wordregs[regbp];

  1856.                 oper2 = 1;

  1857.                 op_sub16();

  1858.                 cf = oldcf;

  1859.                 regs.wordregs[regbp] = res16;

  1860.                 break;

  1861. 

  1862.             case 0x4E:	/* 4E DEC eSI */

  1863.                 oldcf = cf;

  1864.                 oper1 = regs.wordregs[regsi];

  1865.                 oper2 = 1;

  1866.                 op_sub16();

  1867.                 cf = oldcf;

  1868.                 regs.wordregs[regsi] = res16;

  1869.                 break;

  1870. 

  1871.             case 0x4F:	/* 4F DEC eDI */

  1872.                 oldcf = cf;

  1873.                 oper1 = regs.wordregs[regdi];

  1874.                 oper2 = 1;

  1875.                 op_sub16();

  1876.                 cf = oldcf;

  1877.                 regs.wordregs[regdi] = res16;

  1878.                 break;

  1879. 

  1880.             case 0x50:	/* 50 PUSH eAX */

  1881.                 push (regs.wordregs[regax]);

  1882.                 break;

  1883. 

  1884.             case 0x51:	/* 51 PUSH eCX */

  1885.                 push (regs.wordregs[regcx]);

  1886.                 break;

  1887. 

  1888.             case 0x52:	/* 52 PUSH eDX */

  1889.                 push (regs.wordregs[regdx]);

  1890.                 break;

  1891. 

  1892.             case 0x53:	/* 53 PUSH eBX */

  1893.                 push (regs.wordregs[regbx]);

  1894.                 break;

  1895. 

  1896.             case 0x54:	/* 54 PUSH eSP */

  1897. #ifdef USE_286_STYLE_PUSH_SP

  1898.                 push (regs.wordregs[regsp]);

  1899. #else

  1900.                 push (regs.wordregs[regsp] - 2);

  1901. #endif

  1902.                 break;

  1903. 

  1904.             case 0x55:	/* 55 PUSH eBP */

  1905.                 push (regs.wordregs[regbp]);

  1906.                 break;

  1907. 

  1908.             case 0x56:	/* 56 PUSH eSI */

  1909.                 push (regs.wordregs[regsi]);

  1910.                 break;

  1911. 

  1912.             case 0x57:	/* 57 PUSH eDI */

  1913.                 push (regs.wordregs[regdi]);

  1914.                 break;

  1915. 

  1916.             case 0x58:	/* 58 POP eAX */

  1917.                 regs.wordregs[regax] = pop();

  1918.                 break;

  1919. 

  1920.             case 0x59:	/* 59 POP eCX */

  1921.                 regs.wordregs[regcx] = pop();

  1922.                 break;

  1923. 

  1924.             case 0x5A:	/* 5A POP eDX */

  1925.                 regs.wordregs[regdx] = pop();

  1926.                 break;

  1927. 

  1928.             case 0x5B:	/* 5B POP eBX */

  1929.                 regs.wordregs[regbx] = pop();

  1930.                 break;

  1931. 

  1932.             case 0x5C:	/* 5C POP eSP */

  1933.                 regs.wordregs[regsp] = pop();

  1934.                 break;

  1935. 

  1936.             case 0x5D:	/* 5D POP eBP */

  1937.                 regs.wordregs[regbp] = pop();

  1938.                 break;

  1939. 

  1940.             case 0x5E:	/* 5E POP eSI */

  1941.                 regs.wordregs[regsi] = pop();

  1942.                 break;

  1943. 

  1944.             case 0x5F:	/* 5F POP eDI */

  1945.                 regs.wordregs[regdi] = pop();

  1946.                 break;

  1947. 

  1948. #ifndef CPU_8086

  1949.             case 0x60:	/* 60 PUSHA (80186+) */

  1950.                 oldsp = regs.wordregs[regsp];

  1951.                 push (regs.wordregs[regax]);

  1952.                 push (regs.wordregs[regcx]);

  1953.                 push (regs.wordregs[regdx]);

  1954.                 push (regs.wordregs[regbx]);

  1955.                 push (oldsp);

  1956.                 push (regs.wordregs[regbp]);

  1957.                 push (regs.wordregs[regsi]);

  1958.                 push (regs.wordregs[regdi]);

  1959.                 break;

  1960. 

  1961.             case 0x61:	/* 61 POPA (80186+) */

  1962.                 regs.wordregs[regdi] = pop();

  1963.                 regs.wordregs[regsi] = pop();

  1964.                 regs.wordregs[regbp] = pop();

  1965.                 dummy = pop();

  1966.                 regs.wordregs[regbx] = pop();

  1967.                 regs.wordregs[regdx] = pop();

  1968.                 regs.wordregs[regcx] = pop();

  1969.                 regs.wordregs[regax] = pop();

  1970.                 break;

  1971. 

  1972.             case 0x62: /* 62 BOUND Gv, Ev (80186+) */

  1973.                 modregrm();

  1974.                 getea (rm);

  1975.                 if (signext32 (getreg16 (reg) ) < signext32 ( getmem16 (ea >> 4, ea & 15) ) ) {

  1976.                         intcall86 (5); //bounds check exception

  1977.                     }

  1978.                 else {

  1979.                         ea += 2;

  1980.                         if (signext32 (getreg16 (reg) ) > signext32 ( getmem16 (ea >> 4, ea & 15) ) ) {

  1981.                                 intcall86(5); //bounds check exception

  1982.                             }

  1983.                     }

  1984.                 break;

  1985. 

  1986.             case 0x68:	/* 68 PUSH Iv (80186+) */

  1987.                 push (getmem16 (segregs[regcs], ip) );

  1988.                 StepIP (2);

  1989.                 break;

  1990. 

  1991.             case 0x69:	/* 69 IMUL Gv Ev Iv (80186+) */

  1992.                 modregrm();

  1993.                 temp1 = readrm16 (rm);

  1994.                 temp2 = getmem16 (segregs[regcs], ip);

  1995.                 StepIP (2);

  1996.                 if ( (temp1 & 0x8000L) == 0x8000L) {

  1997.                         temp1 = temp1 | 0xFFFF0000L;

  1998.                     }

  1999. 

  2000.                 if ( (temp2 & 0x8000L) == 0x8000L) {

  2001.                         temp2 = temp2 | 0xFFFF0000L;

  2002.                     }

  2003. 

  2004.                 temp3 = temp1 * temp2;

  2005.                 putreg16 (reg, temp3 & 0xFFFFL);

  2006.                 if (temp3 & 0xFFFF0000L) {

  2007.                         cf = 1;

  2008.                         of = 1;

  2009.                     }

  2010.                 else {

  2011.                         cf = 0;

  2012.                         of = 0;

  2013.                     }

  2014.                 break;

  2015. 

  2016.             case 0x6A:	/* 6A PUSH Ib (80186+) */

  2017.                 push (getmem8 (segregs[regcs], ip) );

  2018.                 StepIP (1);

  2019.                 break;

  2020. 

  2021.             case 0x6B:	/* 6B IMUL Gv Eb Ib (80186+) */

  2022.                 modregrm();

  2023.                 temp1 = readrm16 (rm);

  2024.                 temp2 = signext (getmem8 (segregs[regcs], ip) );

  2025.                 StepIP (1);

  2026.                 if ( (temp1 & 0x8000L) == 0x8000L) {

  2027.                         temp1 = temp1 | 0xFFFF0000L;

  2028.                     }

  2029. 

  2030.                 if ( (temp2 & 0x8000L) == 0x8000L) {

  2031.                         temp2 = temp2 | 0xFFFF0000L;

  2032.                     }

  2033. 

  2034.                 temp3 = temp1 * temp2;

  2035.                 putreg16 (reg, temp3 & 0xFFFFL);

  2036.                 if (temp3 & 0xFFFF0000L) {

  2037.                         cf = 1;

  2038.                         of = 1;

  2039.                     }

  2040.                 else {

  2041.                         cf = 0;

  2042.                         of = 0;

  2043.                     }

  2044.                 break;

  2045. 

  2046.             case 0x6C:	/* 6E INSB */

  2047.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2048.                         break;

  2049.                     }

  2050. 

  2051.                 putmem8 (useseg, regs.wordregs[regsi], portin (regs.wordregs[regdx]) );

  2052.                 if (df) {

  2053.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2054.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2055.                     }

  2056.                 else {

  2057.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2058.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2059.                     }

  2060. 

  2061.                 if (reptype) {

  2062.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2063.                     }

  2064. 

  2065.                 totalexec++;

  2066.                 loopcount++;

  2067.                 if (!reptype) {

  2068.                         break;

  2069.                     }

  2070. 

  2071.                 ip = firstip;

  2072.                 break;

  2073. 

  2074.             case 0x6D:	/* 6F INSW */

  2075.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2076.                         break;

  2077.                     }

  2078. 

  2079.                 putmem16 (useseg, regs.wordregs[regsi], portin16 (regs.wordregs[regdx]) );

  2080.                 if (df) {

  2081.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2082.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2083.                     }

  2084.                 else {

  2085.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2086.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2087.                     }

  2088. 

  2089.                 if (reptype) {

  2090.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2091.                     }

  2092. 

  2093.                 totalexec++;

  2094.                 loopcount++;

  2095.                 if (!reptype) {

  2096.                         break;

  2097.                     }

  2098. 

  2099.                 ip = firstip;

  2100.                 break;

  2101. 

  2102.             case 0x6E:	/* 6E OUTSB */

  2103.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2104.                         break;

  2105.                     }

  2106. 

  2107.                 portout (regs.wordregs[regdx], getmem8 (useseg, regs.wordregs[regsi]) );

  2108.                 if (df) {

  2109.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2110.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2111.                     }

  2112.                 else {

  2113.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2114.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2115.                     }

  2116. 

  2117.                 if (reptype) {

  2118.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2119.                     }

  2120. 

  2121.                 totalexec++;

  2122.                 loopcount++;

  2123.                 if (!reptype) {

  2124.                         break;

  2125.                     }

  2126. 

  2127.                 ip = firstip;

  2128.                 break;

  2129. 

  2130.             case 0x6F:	/* 6F OUTSW */

  2131.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2132.                         break;

  2133.                     }

  2134. 

  2135.                 portout16 (regs.wordregs[regdx], getmem16 (useseg, regs.wordregs[regsi]) );

  2136.                 if (df) {

  2137.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2138.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2139.                     }

  2140.                 else {

  2141.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2142.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2143.                     }

  2144. 

  2145.                 if (reptype) {

  2146.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2147.                     }

  2148. 

  2149.                 totalexec++;

  2150.                 loopcount++;

  2151.                 if (!reptype) {

  2152.                         break;

  2153.                     }

  2154. 

  2155.                 ip = firstip;

  2156.                 break;

  2157. #endif

  2158. 

  2159.             case 0x70:	/* 70 JO Jb */

  2160.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2161.                 StepIP (1);

  2162.                 if (of) {

  2163.                         ip = ip + temp16;

  2164.                     }

  2165.                 break;

  2166. 

  2167.             case 0x71:	/* 71 JNO Jb */

  2168.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2169.                 StepIP (1);

  2170.                 if (!of) {

  2171.                         ip = ip + temp16;

  2172.                     }

  2173.                 break;

  2174. 

  2175.             case 0x72:	/* 72 JB Jb */

  2176.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2177.                 StepIP (1);

  2178.                 if (cf) {

  2179.                         ip = ip + temp16;

  2180.                     }

  2181.                 break;

  2182. 

  2183.             case 0x73:	/* 73 JNB Jb */

  2184.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2185.                 StepIP (1);

  2186.                 if (!cf) {

  2187.                         ip = ip + temp16;

  2188.                     }

  2189.                 break;

  2190. 

  2191.             case 0x74:	/* 74 JZ Jb */

  2192.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2193.                 StepIP (1);

  2194.                 if (zf) {

  2195.                         ip = ip + temp16;

  2196.                     }

  2197.                 break;

  2198. 

  2199.             case 0x75:	/* 75 JNZ Jb */

  2200.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2201.                 StepIP (1);

  2202.                 if (!zf) {

  2203.                         ip = ip + temp16;

  2204.                     }

  2205.                 break;

  2206. 

  2207.             case 0x76:	/* 76 JBE Jb */

  2208.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2209.                 StepIP (1);

  2210.                 if (cf || zf) {

  2211.                         ip = ip + temp16;

  2212.                     }

  2213.                 break;

  2214. 

  2215.             case 0x77:	/* 77 JA Jb */

  2216.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2217.                 StepIP (1);

  2218.                 if (!cf && !zf) {

  2219.                         ip = ip + temp16;

  2220.                     }

  2221.                 break;

  2222. 

  2223.             case 0x78:	/* 78 JS Jb */

  2224.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2225.                 StepIP (1);

  2226.                 if (sf) {

  2227.                         ip = ip + temp16;

  2228.                     }

  2229.                 break;

  2230. 

  2231.             case 0x79:	/* 79 JNS Jb */

  2232.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2233.                 StepIP (1);

  2234.                 if (!sf) {

  2235.                         ip = ip + temp16;

  2236.                     }

  2237.                 break;

  2238. 

  2239.             case 0x7A:	/* 7A JPE Jb */

  2240.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2241.                 StepIP (1);

  2242.                 if (pf) {

  2243.                         ip = ip + temp16;

  2244.                     }

  2245.                 break;

  2246. 

  2247.             case 0x7B:	/* 7B JPO Jb */

  2248.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2249.                 StepIP (1);

  2250.                 if (!pf) {

  2251.                         ip = ip + temp16;

  2252.                     }

  2253.                 break;

  2254. 

  2255.             case 0x7C:	/* 7C JL Jb */

  2256.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2257.                 StepIP (1);

  2258.                 if (sf != of) {

  2259.                         ip = ip + temp16;

  2260.                     }

  2261.                 break;

  2262. 

  2263.             case 0x7D:	/* 7D JGE Jb */

  2264.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2265.                 StepIP (1);

  2266.                 if (sf == of) {

  2267.                         ip = ip + temp16;

  2268.                     }

  2269.                 break;

  2270. 

  2271.             case 0x7E:	/* 7E JLE Jb */

  2272.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2273.                 StepIP (1);

  2274.                 if ( (sf != of) || zf) {

  2275.                         ip = ip + temp16;

  2276.                     }

  2277.                 break;

  2278. 

  2279.             case 0x7F:	/* 7F JG Jb */

  2280.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2281.                 StepIP (1);

  2282.                 if (!zf && (sf == of) ) {

  2283.                         ip = ip + temp16;

  2284.                     }

  2285.                 break;

  2286. 

  2287.             case 0x80:

  2288.             case 0x82:	/* 80/82 GRP1 Eb Ib */

  2289.                 modregrm();

  2290.                 oper1b = readrm8 (rm);

  2291.                 oper2b = getmem8 (segregs[regcs], ip);

  2292.                 StepIP (1);

  2293.                 switch (reg) {

  2294.                         case 0:

  2295.                             op_add8();

  2296.                             break;

  2297.                         case 1:

  2298.                             op_or8();

  2299.                             break;

  2300.                         case 2:

  2301.                             op_adc8();

  2302.                             break;

  2303.                         case 3:

  2304.                             op_sbb8();

  2305.                             break;

  2306.                         case 4:

  2307.                             op_and8();

  2308.                             break;

  2309.                         case 5:

  2310.                             op_sub8();

  2311.                             break;

  2312.                         case 6:

  2313.                             op_xor8();

  2314.                             break;

  2315.                         case 7:

  2316.                             flag_sub8 (oper1b, oper2b);

  2317.                             break;

  2318.                         default:

  2319.                             break;	/* to avoid compiler warnings */

  2320.                     }

  2321. 

  2322.                 if (reg < 7) {

  2323.                         writerm8 (rm, res8);

  2324.                     }

  2325.                 break;

  2326. 

  2327.             case 0x81:	/* 81 GRP1 Ev Iv */

  2328.             case 0x83:	/* 83 GRP1 Ev Ib */

  2329.                 modregrm();

  2330.                 oper1 = readrm16 (rm);

  2331.                 if (opcode == 0x81) {

  2332.                         oper2 = getmem16 (segregs[regcs], ip);

  2333.                         StepIP (2);

  2334.                     }

  2335.                 else {

  2336.                         oper2 = signext (getmem8 (segregs[regcs], ip) );

  2337.                         StepIP (1);

  2338.                     }

  2339. 

  2340.                 switch (reg) {

  2341.                         case 0:

  2342.                             op_add16();

  2343.                             break;

  2344.                         case 1:

  2345.                             op_or16();

  2346.                             break;

  2347.                         case 2:

  2348.                             op_adc16();

  2349.                             break;

  2350.                         case 3:

  2351.                             op_sbb16();

  2352.                             break;

  2353.                         case 4:

  2354.                             op_and16();

  2355.                             break;

  2356.                         case 5:

  2357.                             op_sub16();

  2358.                             break;

  2359.                         case 6:

  2360.                             op_xor16();

  2361.                             break;

  2362.                         case 7:

  2363.                             flag_sub16 (oper1, oper2);

  2364.                             break;

  2365.                         default:

  2366.                             break;	/* to avoid compiler warnings */

  2367.                     }

  2368. 

  2369.                 if (reg < 7) {

  2370.                         writerm16 (rm, res16);

  2371.                     }

  2372.                 break;

  2373. 

  2374.             case 0x84:	/* 84 TEST Gb Eb */

  2375.                 modregrm();

  2376.                 oper1b = getreg8 (reg);

  2377.                 oper2b = readrm8 (rm);

  2378.                 flag_log8 (oper1b & oper2b);

  2379.                 break;

  2380. 

  2381.             case 0x85:	/* 85 TEST Gv Ev */

  2382.                 modregrm();

  2383.                 oper1 = getreg16 (reg);

  2384.                 oper2 = readrm16 (rm);

  2385.                 flag_log16 (oper1 & oper2);

  2386.                 break;

  2387. 

  2388.             case 0x86:	/* 86 XCHG Gb Eb */

  2389.                 modregrm();

  2390.                 oper1b = getreg8 (reg);

  2391.                 putreg8 (reg, readrm8 (rm) );

  2392.                 writerm8 (rm, oper1b);

  2393.                 break;

  2394. 

  2395.             case 0x87:	/* 87 XCHG Gv Ev */

  2396.                 modregrm();

  2397.                 oper1 = getreg16 (reg);

  2398.                 putreg16 (reg, readrm16 (rm) );

  2399.                 writerm16 (rm, oper1);

  2400.                 break;

  2401. 

  2402.             case 0x88:	/* 88 MOV Eb Gb */

  2403.                 modregrm();

  2404.                 writerm8 (rm, getreg8 (reg) );

  2405.                 break;

  2406. 

  2407.             case 0x89:	/* 89 MOV Ev Gv */

  2408.                 modregrm();

  2409.                 writerm16 (rm, getreg16 (reg) );

  2410.                 break;

  2411. 

  2412.             case 0x8A:	/* 8A MOV Gb Eb */

  2413.                 modregrm();

  2414.                 putreg8 (reg, readrm8 (rm) );

  2415.                 break;

  2416. 

  2417.             case 0x8B:	/* 8B MOV Gv Ev */

  2418.                 modregrm();

  2419.                 putreg16 (reg, readrm16 (rm) );

  2420.                 break;

  2421. 

  2422.             case 0x8C:	/* 8C MOV Ew Sw */

  2423.                 modregrm();

  2424.                 writerm16 (rm, getsegreg (reg) );

  2425.                 break;

  2426. 

  2427.             case 0x8D:	/* 8D LEA Gv M */

  2428.                 modregrm();

  2429.                 getea (rm);

  2430.                 putreg16 (reg, ea - segbase (useseg) );

  2431.                 break;

  2432. 

  2433.             case 0x8E:	/* 8E MOV Sw Ew */

  2434.                 modregrm();

  2435.                 putsegreg (reg, readrm16 (rm) );

  2436.                 break;

  2437. 

  2438.             case 0x8F:	/* 8F POP Ev */

  2439.                 modregrm();

  2440.                 writerm16 (rm, pop() );

  2441.                 break;

  2442. 

  2443.             case 0x90:	/* 90 NOP */

  2444.                 break;

  2445. 

  2446.             case 0x91:	/* 91 XCHG eCX eAX */

  2447.                 oper1 = regs.wordregs[regcx];

  2448.                 regs.wordregs[regcx] = regs.wordregs[regax];

  2449.                 regs.wordregs[regax] = oper1;

  2450.                 break;

  2451. 

  2452.             case 0x92:	/* 92 XCHG eDX eAX */

  2453.                 oper1 = regs.wordregs[regdx];

  2454.                 regs.wordregs[regdx] = regs.wordregs[regax];

  2455.                 regs.wordregs[regax] = oper1;

  2456.                 break;

  2457. 

  2458.             case 0x93:	/* 93 XCHG eBX eAX */

  2459.                 oper1 = regs.wordregs[regbx];

  2460.                 regs.wordregs[regbx] = regs.wordregs[regax];

  2461.                 regs.wordregs[regax] = oper1;

  2462.                 break;

  2463. 

  2464.             case 0x94:	/* 94 XCHG eSP eAX */

  2465.                 oper1 = regs.wordregs[regsp];

  2466.                 regs.wordregs[regsp] = regs.wordregs[regax];

  2467.                 regs.wordregs[regax] = oper1;

  2468.                 break;

  2469. 

  2470.             case 0x95:	/* 95 XCHG eBP eAX */

  2471.                 oper1 = regs.wordregs[regbp];

  2472.                 regs.wordregs[regbp] = regs.wordregs[regax];

  2473.                 regs.wordregs[regax] = oper1;

  2474.                 break;

  2475. 

  2476.             case 0x96:	/* 96 XCHG eSI eAX */

  2477.                 oper1 = regs.wordregs[regsi];

  2478.                 regs.wordregs[regsi] = regs.wordregs[regax];

  2479.                 regs.wordregs[regax] = oper1;

  2480.                 break;

  2481. 

  2482.             case 0x97:	/* 97 XCHG eDI eAX */

  2483.                 oper1 = regs.wordregs[regdi];

  2484.                 regs.wordregs[regdi] = regs.wordregs[regax];

  2485.                 regs.wordregs[regax] = oper1;

  2486.                 break;

  2487. 

  2488.             case 0x98:	/* 98 CBW */

  2489.                 if ( (regs.byteregs[regal] & 0x80) == 0x80) {

  2490.                         regs.byteregs[regah] = 0xFF;

  2491.                     }

  2492.                 else {

  2493.                         regs.byteregs[regah] = 0;

  2494.                     }

  2495.                 break;

  2496. 

  2497.             case 0x99:	/* 99 CWD */

  2498.                 if ( (regs.byteregs[regah] & 0x80) == 0x80) {

  2499.                         regs.wordregs[regdx] = 0xFFFF;

  2500.                     }

  2501.                 else {

  2502.                         regs.wordregs[regdx] = 0;

  2503.                     }

  2504.                 break;

  2505. 

  2506.             case 0x9A:	/* 9A CALL Ap */

  2507.                 oper1 = getmem16 (segregs[regcs], ip);

  2508.                 StepIP (2);

  2509.                 oper2 = getmem16 (segregs[regcs], ip);

  2510.                 StepIP (2);

  2511.                 push (segregs[regcs]);

  2512.                 push (ip);

  2513.                 ip = oper1;

  2514.                 segregs[regcs] = oper2;

  2515.                 break;

  2516. 

  2517.             case 0x9B:	/* 9B WAIT */

  2518.                 break;

  2519. 

  2520.             case 0x9C:	/* 9C PUSHF */

  2521.                 push (makeflagsword() | 0xF800);

  2522.                 break;

  2523. 

  2524.             case 0x9D:	/* 9D POPF */

  2525.                 temp16 = pop();

  2526.                 decodeflagsword (temp16);

  2527.                 break;

  2528. 

  2529.             case 0x9E:	/* 9E SAHF */

  2530.                 decodeflagsword ( (makeflagsword() & 0xFF00) | regs.byteregs[regah]);

  2531.                 break;

  2532. 

  2533.             case 0x9F:	/* 9F LAHF */

  2534.                 regs.byteregs[regah] = makeflagsword() & 0xFF;

  2535.                 break;

  2536. 

  2537.             case 0xA0:	/* A0 MOV regs.byteregs[regal] Ob */

  2538.                 regs.byteregs[regal] = getmem8 (useseg, getmem16 (segregs[regcs], ip) );

  2539.                 StepIP (2);

  2540.                 break;

  2541. 

  2542.             case 0xA1:	/* A1 MOV eAX Ov */

  2543.                 oper1 = getmem16 (useseg, getmem16 (segregs[regcs], ip) );

  2544.                 StepIP (2);

  2545.                 regs.wordregs[regax] = oper1;

  2546.                 break;

  2547. 

  2548.             case 0xA2:	/* A2 MOV Ob regs.byteregs[regal] */

  2549.                 putmem8 (useseg, getmem16 (segregs[regcs], ip), regs.byteregs[regal]);

  2550.                 StepIP (2);

  2551.                 break;

  2552. 

  2553.             case 0xA3:	/* A3 MOV Ov eAX */

  2554.                 putmem16 (useseg, getmem16 (segregs[regcs], ip), regs.wordregs[regax]);

  2555.                 StepIP (2);

  2556.                 break;

  2557. 

  2558.             case 0xA4:	/* A4 MOVSB */

  2559.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2560.                         break;

  2561.                     }

  2562. 

  2563.                 putmem8 (segregs[reges], regs.wordregs[regdi], getmem8 (useseg, regs.wordregs[regsi]) );

  2564.                 if (df) {

  2565.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2566.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2567.                     }

  2568.                 else {

  2569.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2570.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2571.                     }

  2572. 

  2573.                 if (reptype) {

  2574.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2575.                     }

  2576. 

  2577.                 totalexec++;

  2578.                 loopcount++;

  2579.                 if (!reptype) {

  2580.                         break;

  2581.                     }

  2582. 

  2583.                 ip = firstip;

  2584.                 break;

  2585. 

  2586.             case 0xA5:	/* A5 MOVSW */

  2587.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2588.                         break;

  2589.                     }

  2590. 

  2591.                 putmem16 (segregs[reges], regs.wordregs[regdi], getmem16 (useseg, regs.wordregs[regsi]) );

  2592.                 if (df) {

  2593.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2594.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2595.                     }

  2596.                 else {

  2597.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2598.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2599.                     }

  2600. 

  2601.                 if (reptype) {

  2602.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2603.                     }

  2604. 

  2605.                 totalexec++;

  2606.                 loopcount++;

  2607.                 if (!reptype) {

  2608.                         break;

  2609.                     }

  2610. 

  2611.                 ip = firstip;

  2612.                 break;

  2613. 

  2614.             case 0xA6:	/* A6 CMPSB */

  2615.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2616.                         break;

  2617.                     }

  2618. 

  2619.                 oper1b = getmem8 (useseg, regs.wordregs[regsi]);

  2620.                 oper2b = getmem8 (segregs[reges], regs.wordregs[regdi]);

  2621.                 if (df) {

  2622.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2623.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2624.                     }

  2625.                 else {

  2626.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2627.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2628.                     }

  2629. 

  2630.                 flag_sub8 (oper1b, oper2b);

  2631.                 if (reptype) {

  2632.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2633.                     }

  2634. 

  2635.                 if ( (reptype == 1) && !zf) {

  2636.                         break;

  2637.                     }

  2638.                 else if ( (reptype == 2) && (zf == 1) ) {

  2639.                         break;

  2640.                     }

  2641. 

  2642.                 totalexec++;

  2643.                 loopcount++;

  2644.                 if (!reptype) {

  2645.                         break;

  2646.                     }

  2647. 

  2648.                 ip = firstip;

  2649.                 break;

  2650. 

  2651.             case 0xA7:	/* A7 CMPSW */

  2652.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2653.                         break;

  2654.                     }

  2655. 

  2656.                 oper1 = getmem16 (useseg,regs.wordregs[regsi]);

  2657.                 oper2 = getmem16 (segregs[reges], regs.wordregs[regdi]);

  2658.                 if (df) {

  2659.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2660.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2661.                     }

  2662.                 else {

  2663.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2664.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2665.                     }

  2666. 

  2667.                 flag_sub16 (oper1, oper2);

  2668.                 if (reptype) {

  2669.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2670.                     }

  2671. 

  2672.                 if ( (reptype == 1) && !zf) {

  2673.                         break;

  2674.                     }

  2675. 

  2676.                 if ( (reptype == 2) && (zf == 1) ) {

  2677.                         break;

  2678.                     }

  2679. 

  2680.                 totalexec++;

  2681.                 loopcount++;

  2682.                 if (!reptype) {

  2683.                         break;

  2684.                     }

  2685. 

  2686.                 ip = firstip;

  2687.                 break;

  2688. 

  2689.             case 0xA8:	/* A8 TEST regs.byteregs[regal] Ib */

  2690.                 oper1b = regs.byteregs[regal];

  2691.                 oper2b = getmem8 (segregs[regcs], ip);

  2692.                 StepIP (1);

  2693.                 flag_log8 (oper1b & oper2b);

  2694.                 break;

  2695. 

  2696.             case 0xA9:	/* A9 TEST eAX Iv */

  2697.                 oper1 = regs.wordregs[regax];

  2698.                 oper2 = getmem16 (segregs[regcs], ip);

  2699.                 StepIP (2);

  2700.                 flag_log16 (oper1 & oper2);

  2701.                 break;

  2702. 

  2703.             case 0xAA:	/* AA STOSB */

  2704.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2705.                         break;

  2706.                     }

  2707. 

  2708.                 putmem8 (segregs[reges], regs.wordregs[regdi], regs.byteregs[regal]);

  2709.                 if (df) {

  2710.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2711.                     }

  2712.                 else {

  2713.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2714.                     }

  2715. 

  2716.                 if (reptype) {

  2717.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2718.                     }

  2719. 

  2720.                 totalexec++;

  2721.                 loopcount++;

  2722.                 if (!reptype) {

  2723.                         break;

  2724.                     }

  2725. 

  2726.                 ip = firstip;

  2727.                 break;

  2728. 

  2729.             case 0xAB:	/* AB STOSW */

  2730.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2731.                         break;

  2732.                     }

  2733. 

  2734.                 putmem16 (segregs[reges], regs.wordregs[regdi], regs.wordregs[regax]);

  2735.                 if (df) {

  2736.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2737.                     }

  2738.                 else {

  2739.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2740.                     }

  2741. 

  2742.                 if (reptype) {

  2743.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2744.                     }

  2745. 

  2746.                 totalexec++;

  2747.                 loopcount++;

  2748.                 if (!reptype) {

  2749.                         break;

  2750.                     }

  2751. 

  2752.                 ip = firstip;

  2753.                 break;

  2754. 

  2755.             case 0xAC:	/* AC LODSB */

  2756.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2757.                         break;

  2758.                     }

  2759. 

  2760.                 regs.byteregs[regal] = getmem8 (useseg, regs.wordregs[regsi]);

  2761.                 if (df) {

  2762.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2763.                     }

  2764.                 else {

  2765.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2766.                     }

  2767. 

  2768.                 if (reptype) {

  2769.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2770.                     }

  2771. 

  2772.                 totalexec++;

  2773.                 loopcount++;

  2774.                 if (!reptype) {

  2775.                         break;

  2776.                     }

  2777. 

  2778.                 ip = firstip;

  2779.                 break;

  2780. 

  2781.             case 0xAD:	/* AD LODSW */

  2782.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2783.                         break;

  2784.                     }

  2785. 

  2786.                 oper1 = getmem16 (useseg, regs.wordregs[regsi]);

  2787.                 regs.wordregs[regax] = oper1;

  2788.                 if (df) {

  2789.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2790.                     }

  2791.                 else {

  2792.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2793.                     }

  2794. 

  2795.                 if (reptype) {

  2796.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2797.                     }

  2798. 

  2799.                 totalexec++;

  2800.                 loopcount++;

  2801.                 if (!reptype) {

  2802.                         break;

  2803.                     }

  2804. 

  2805.                 ip = firstip;

  2806.                 break;

  2807. 

  2808.             case 0xAE:	/* AE SCASB */

  2809.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2810.                         break;

  2811.                     }

  2812. 

  2813.                 oper1b = regs.byteregs[regal];

  2814.                 oper2b = getmem8 (segregs[reges], regs.wordregs[regdi]);

  2815.                 flag_sub8 (oper1b, oper2b);

  2816.                 if (df) {

  2817.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2818.                     }

  2819.                 else {

  2820.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2821.                     }

  2822. 

  2823.                 if (reptype) {

  2824.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2825.                     }

  2826. 

  2827.                 if ( (reptype == 1) && !zf) {

  2828.                         break;

  2829.                     }

  2830.                 else if ( (reptype == 2) && (zf == 1) ) {

  2831.                         break;

  2832.                     }

  2833. 

  2834.                 totalexec++;

  2835.                 loopcount++;

  2836.                 if (!reptype) {

  2837.                         break;

  2838.                     }

  2839. 

  2840.                 ip = firstip;

  2841.                 break;

  2842. 

  2843.             case 0xAF:	/* AF SCASW */

  2844.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2845.                         break;

  2846.                     }

  2847. 

  2848.                 oper1 = regs.wordregs[regax];

  2849.                 oper2 = getmem16 (segregs[reges], regs.wordregs[regdi]);

  2850.                 flag_sub16 (oper1, oper2);

  2851.                 if (df) {

  2852.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2853.                     }

  2854.                 else {

  2855.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2856.                     }

  2857. 

  2858.                 if (reptype) {

  2859.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2860.                     }

  2861. 

  2862.                 if ( (reptype == 1) && !zf) {

  2863.                         break;

  2864.                     }

  2865.                 else if ( (reptype == 2) & (zf == 1) ) {

  2866.                         break;

  2867.                     }

  2868. 

  2869.                 totalexec++;

  2870.                 loopcount++;

  2871.                 if (!reptype) {

  2872.                         break;

  2873.                     }

  2874. 

  2875.                 ip = firstip;

  2876.                 break;

  2877. 

  2878.             case 0xB0:	/* B0 MOV regs.byteregs[regal] Ib */

  2879.                 regs.byteregs[regal] = getmem8 (segregs[regcs], ip);

  2880.                 StepIP (1);

  2881.                 break;

  2882. 

  2883.             case 0xB1:	/* B1 MOV regs.byteregs[regcl] Ib */

  2884.                 regs.byteregs[regcl] = getmem8 (segregs[regcs], ip);

  2885.                 StepIP (1);

  2886.                 break;

  2887. 

  2888.             case 0xB2:	/* B2 MOV regs.byteregs[regdl] Ib */

  2889.                 regs.byteregs[regdl] = getmem8 (segregs[regcs], ip);

  2890.                 StepIP (1);

  2891.                 break;

  2892. 

  2893.             case 0xB3:	/* B3 MOV regs.byteregs[regbl] Ib */

  2894.                 regs.byteregs[regbl] = getmem8 (segregs[regcs], ip);

  2895.                 StepIP (1);

  2896.                 break;

  2897. 

  2898.             case 0xB4:	/* B4 MOV regs.byteregs[regah] Ib */

  2899.                 regs.byteregs[regah] = getmem8 (segregs[regcs], ip);

  2900.                 StepIP (1);

  2901.                 break;

  2902. 

  2903.             case 0xB5:	/* B5 MOV regs.byteregs[regch] Ib */

  2904.                 regs.byteregs[regch] = getmem8 (segregs[regcs], ip);

  2905.                 StepIP (1);

  2906.                 break;

  2907. 

  2908.             case 0xB6:	/* B6 MOV regs.byteregs[regdh] Ib */

  2909.                 regs.byteregs[regdh] = getmem8 (segregs[regcs], ip);

  2910.                 StepIP (1);

  2911.                 break;

  2912. 

  2913.             case 0xB7:	/* B7 MOV regs.byteregs[regbh] Ib */

  2914.                 regs.byteregs[regbh] = getmem8 (segregs[regcs], ip);

  2915.                 StepIP (1);

  2916.                 break;

  2917. 

  2918.             case 0xB8:	/* B8 MOV eAX Iv */

  2919.                 oper1 = getmem16 (segregs[regcs], ip);

  2920.                 StepIP (2);

  2921.                 regs.wordregs[regax] = oper1;

  2922.                 break;

  2923. 

  2924.             case 0xB9:	/* B9 MOV eCX Iv */

  2925.                 oper1 = getmem16 (segregs[regcs], ip);

  2926.                 StepIP (2);

  2927.                 regs.wordregs[regcx] = oper1;

  2928.                 break;

  2929. 

  2930.             case 0xBA:	/* BA MOV eDX Iv */

  2931.                 oper1 = getmem16 (segregs[regcs], ip);

  2932.                 StepIP (2);

  2933.                 regs.wordregs[regdx] = oper1;

  2934.                 break;

  2935. 

  2936.             case 0xBB:	/* BB MOV eBX Iv */

  2937.                 oper1 = getmem16 (segregs[regcs], ip);

  2938.                 StepIP (2);

  2939.                 regs.wordregs[regbx] = oper1;

  2940.                 break;

  2941. 

  2942.             case 0xBC:	/* BC MOV eSP Iv */

  2943.                 regs.wordregs[regsp] = getmem16 (segregs[regcs], ip);

  2944.                 StepIP (2);

  2945.                 break;

  2946. 

  2947.             case 0xBD:	/* BD MOV eBP Iv */

  2948.                 regs.wordregs[regbp] = getmem16 (segregs[regcs], ip);

  2949.                 StepIP (2);

  2950.                 break;

  2951. 

  2952.             case 0xBE:	/* BE MOV eSI Iv */

  2953.                 regs.wordregs[regsi] = getmem16 (segregs[regcs], ip);

  2954.                 StepIP (2);

  2955.                 break;

  2956. 

  2957.             case 0xBF:	/* BF MOV eDI Iv */

  2958.                 regs.wordregs[regdi] = getmem16 (segregs[regcs], ip);

  2959.                 StepIP (2);

  2960.                 break;

  2961. 

  2962.             case 0xC0:	/* C0 GRP2 byte imm8 (80186+) */

  2963.                 modregrm();

  2964.                 oper1b = readrm8 (rm);

  2965.                 oper2b = getmem8 (segregs[regcs], ip);

  2966.                 StepIP (1);

  2967.                 writerm8 (rm, op_grp2_8 (oper2b) );

  2968.                 break;

  2969. 

  2970.             case 0xC1:	/* C1 GRP2 word imm8 (80186+) */

  2971.                 modregrm();

  2972.                 oper1 = readrm16 (rm);

  2973.                 oper2 = getmem8 (segregs[regcs], ip);

  2974.                 StepIP (1);

  2975.                 writerm16 (rm, op_grp2_16 ( (uint8_t) oper2) );

  2976.                 break;

  2977. 

  2978.             case 0xC2:	/* C2 RET Iw */

  2979.                 oper1 = getmem16 (segregs[regcs], ip);

  2980.                 ip = pop();

  2981.                 regs.wordregs[regsp] = regs.wordregs[regsp] + oper1;

  2982.                 break;

  2983. 

  2984.             case 0xC3:	/* C3 RET */

  2985.                 ip = pop();

  2986.                 break;

  2987. 

  2988.             case 0xC4:	/* C4 LES Gv Mp */

  2989.                 modregrm();

  2990.                 getea (rm);

  2991.                 putreg16 (reg, read86 (ea) + read86 (ea + 1) * 256);

  2992.                 segregs[reges] = read86 (ea + 2) + read86 (ea + 3) * 256;

  2993.                 break;

  2994. 

  2995.             case 0xC5:	/* C5 LDS Gv Mp */

  2996.                 modregrm();

  2997.                 getea (rm);

  2998.                 putreg16 (reg, read86 (ea) + read86 (ea + 1) * 256);

  2999.                 segregs[regds] = read86 (ea + 2) + read86 (ea + 3) * 256;

  3000.                 break;

  3001. 

  3002.             case 0xC6:	/* C6 MOV Eb Ib */

  3003.                 modregrm();

  3004.                 writerm8 (rm, getmem8 (segregs[regcs], ip) );

  3005.                 StepIP (1);

  3006.                 break;

  3007. 

  3008.             case 0xC7:	/* C7 MOV Ev Iv */

  3009.                 modregrm();

  3010.                 writerm16 (rm, getmem16 (segregs[regcs], ip) );

  3011.                 StepIP (2);

  3012.                 break;

  3013. 

  3014.             case 0xC8:	/* C8 ENTER (80186+) */

  3015.                 stacksize = getmem16 (segregs[regcs], ip);

  3016.                 StepIP (2);

  3017.                 nestlev = getmem8 (segregs[regcs], ip);

  3018.                 StepIP (1);

  3019.                 push (regs.wordregs[regbp]);

  3020.                 frametemp = regs.wordregs[regsp];

  3021.                 if (nestlev) {

  3022.                         for (temp16 = 1; temp16 < nestlev; temp16++) {

  3023.                                 regs.wordregs[regbp] = regs.wordregs[regbp] - 2;

  3024.                                 push (regs.wordregs[regbp]);

  3025.                             }

  3026. 

  3027.                         push (regs.wordregs[regsp]);

  3028.                     }

  3029. 

  3030.                 regs.wordregs[regbp] = frametemp;

  3031.                 regs.wordregs[regsp] = regs.wordregs[regbp] - stacksize;

  3032. 

  3033.                 break;

  3034. 

  3035.             case 0xC9:	/* C9 LEAVE (80186+) */

  3036.                 regs.wordregs[regsp] = regs.wordregs[regbp];

  3037.                 regs.wordregs[regbp] = pop();

  3038.                 break;

  3039. 

  3040.             case 0xCA:	/* CA RETF Iw */

  3041.                 oper1 = getmem16 (segregs[regcs], ip);

  3042.                 ip = pop();

  3043.                 segregs[regcs] = pop();

  3044.                 regs.wordregs[regsp] = regs.wordregs[regsp] + oper1;

  3045.                 break;

  3046. 

  3047.             case 0xCB:	/* CB RETF */

  3048.                 ip = pop();;

  3049.                 segregs[regcs] = pop();

  3050.                 break;

  3051. 

  3052.             case 0xCC:	/* CC INT 3 */

  3053.                 intcall86 (3);

  3054.                 break;

  3055. 

  3056.             case 0xCD:	/* CD INT Ib */

  3057.                 oper1b = getmem8 (segregs[regcs], ip);

  3058.                 StepIP (1);

  3059.                 intcall86 (oper1b);

  3060.                 break;

  3061. 

  3062.             case 0xCE:	/* CE INTO */

  3063.                 if (of) {

  3064.                         intcall86 (4);

  3065.                     }

  3066.                 break;

  3067. 

  3068.             case 0xCF:	/* CF IRET */

  3069.                 ip = pop();

  3070.                 segregs[regcs] = pop();

  3071.                 decodeflagsword (pop() );

  3072. 

  3073.                 /*

  3074.                  * if (net.enabled) net.canrecv = 1;

  3075.                  */

  3076.                 break;

  3077. 

  3078.             case 0xD0:	/* D0 GRP2 Eb 1 */

  3079.                 modregrm();

  3080.                 oper1b = readrm8 (rm);

  3081.                 writerm8 (rm, op_grp2_8 (1) );

  3082.                 break;

  3083. 

  3084.             case 0xD1:	/* D1 GRP2 Ev 1 */

  3085.                 modregrm();

  3086.                 oper1 = readrm16 (rm);

  3087.                 writerm16 (rm, op_grp2_16 (1) );

  3088.                 break;

  3089. 

  3090.             case 0xD2:	/* D2 GRP2 Eb regs.byteregs[regcl] */

  3091.                 modregrm();

  3092.                 oper1b = readrm8 (rm);

  3093.                 writerm8 (rm, op_grp2_8 (regs.byteregs[regcl]) );

  3094.                 break;

  3095. 

  3096.             case 0xD3:	/* D3 GRP2 Ev regs.byteregs[regcl] */

  3097.                 modregrm();

  3098.                 oper1 = readrm16 (rm);

  3099.                 writerm16 (rm, op_grp2_16 (regs.byteregs[regcl]) );

  3100.                 break;

  3101. 

  3102.             case 0xD4:	/* D4 AAM I0 */

  3103.                 oper1 = getmem8 (segregs[regcs], ip);

  3104.                 StepIP (1);

  3105.                 if (!oper1) {

  3106.                         intcall86 (0);

  3107.                         break;

  3108.                     }	/* division by zero */

  3109. 

  3110.                 regs.byteregs[regah] = (regs.byteregs[regal] / oper1) & 255;

  3111.                 regs.byteregs[regal] = (regs.byteregs[regal] % oper1) & 255;

  3112.                 flag_szp16 (regs.wordregs[regax]);

  3113.                 break;

  3114. 

  3115.             case 0xD5:	/* D5 AAD I0 */

  3116.                 oper1 = getmem8 (segregs[regcs], ip);

  3117.                 StepIP (1);

  3118.                 regs.byteregs[regal] = (regs.byteregs[regah] * oper1 + regs.byteregs[regal]) & 255;

  3119.                 regs.byteregs[regah] = 0;

  3120.                 flag_szp16 (regs.byteregs[regah] * oper1 + regs.byteregs[regal]);

  3121.                 sf = 0;

  3122.                 break;

  3123. 

  3124.             case 0xD6:	/* D6 XLAT on V20/V30, SALC on 8086/8088 */

  3125.             case 0xD7:	/* D7 XLAT */

  3126.                 regs.byteregs[regal] = read86(useseg * 16 + (regs.wordregs[regbx]) + regs.byteregs[regal]);

  3127.                 break;

  3128. 

  3129.             case 0xD8:

  3130.             case 0xD9:

  3131.             case 0xDA:

  3132.             case 0xDB:

  3133.             case 0xDC:

  3134.             case 0xDE:

  3135.             case 0xDD:

  3136.             case 0xDF:	/* escape to x87 FPU (unsupported) */

  3137.                 modregrm();

  3138.                 break;

  3139. 

  3140.             case 0xE0:	/* E0 LOOPNZ Jb */

  3141.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3142.                 StepIP (1);

  3143.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3144.                 if ( (regs.wordregs[regcx]) && !zf) {

  3145.                         ip = ip + temp16;

  3146.                     }

  3147.                 break;

  3148. 

  3149.             case 0xE1:	/* E1 LOOPZ Jb */

  3150.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3151.                 StepIP (1);

  3152.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3153.                 if (regs.wordregs[regcx] && (zf == 1) ) {

  3154.                         ip = ip + temp16;

  3155.                     }

  3156.                 break;

  3157. 

  3158.             case 0xE2:	/* E2 LOOP Jb */

  3159.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3160.                 StepIP (1);

  3161.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3162.                 if (regs.wordregs[regcx]) {

  3163.                         ip = ip + temp16;

  3164.                     }

  3165.                 break;

  3166. 

  3167.             case 0xE3:	/* E3 JCXZ Jb */

  3168.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3169.                 StepIP (1);

  3170.                 if (!regs.wordregs[regcx]) {

  3171.                         ip = ip + temp16;

  3172.                     }

  3173.                 break;

  3174. 

  3175.             case 0xE4:	/* E4 IN regs.byteregs[regal] Ib */

  3176.                 oper1b = getmem8 (segregs[regcs], ip);

  3177.                 StepIP (1);

  3178.                 regs.byteregs[regal] = (uint8_t) portin (oper1b);

  3179.                 break;

  3180. 

  3181.             case 0xE5:	/* E5 IN eAX Ib */

  3182.                 oper1b = getmem8 (segregs[regcs], ip);

  3183.                 StepIP (1);

  3184.                 regs.wordregs[regax] = portin16 (oper1b);

  3185.                 break;

  3186. 

  3187.             case 0xE6:	/* E6 OUT Ib regs.byteregs[regal] */

  3188.                 oper1b = getmem8 (segregs[regcs], ip);

  3189.                 StepIP (1);

  3190.                 portout (oper1b, regs.byteregs[regal]);

  3191.                 break;

  3192. 

  3193.             case 0xE7:	/* E7 OUT Ib eAX */

  3194.                 oper1b = getmem8 (segregs[regcs], ip);

  3195.                 StepIP (1);

  3196.                 portout16 (oper1b, regs.wordregs[regax]);

  3197.                 break;

  3198. 

  3199.             case 0xE8:	/* E8 CALL Jv */

  3200.                 oper1 = getmem16 (segregs[regcs], ip);

  3201.                 StepIP (2);

  3202.                 push (ip);

  3203.                 ip = ip + oper1;

  3204.                 break;

  3205. 

  3206.             case 0xE9:	/* E9 JMP Jv */

  3207.                 oper1 = getmem16 (segregs[regcs], ip);

  3208.                 StepIP (2);

  3209.                 ip = ip + oper1;

  3210.                 break;

  3211. 

  3212.             case 0xEA:	/* EA JMP Ap */

  3213.                 oper1 = getmem16 (segregs[regcs], ip);

  3214.                 StepIP (2);

  3215.                 oper2 = getmem16 (segregs[regcs], ip);

  3216.                 ip = oper1;

  3217.                 segregs[regcs] = oper2;

  3218.                 break;

  3219. 

  3220.             case 0xEB:	/* EB JMP Jb */

  3221.                 oper1 = signext (getmem8 (segregs[regcs], ip) );

  3222.                 StepIP (1);

  3223.                 ip = ip + oper1;

  3224.                 break;

  3225. 

  3226.             case 0xEC:	/* EC IN regs.byteregs[regal] regdx */

  3227.                 oper1 = regs.wordregs[regdx];

  3228.                 regs.byteregs[regal] = (uint8_t) portin (oper1);

  3229.                 break;

  3230. 

  3231.             case 0xED:	/* ED IN eAX regdx */

  3232.                 oper1 = regs.wordregs[regdx];

  3233.                 regs.wordregs[regax] = portin16 (oper1);

  3234.                 break;

  3235. 

  3236.             case 0xEE:	/* EE OUT regdx regs.byteregs[regal] */

  3237.                 oper1 = regs.wordregs[regdx];

  3238.                 portout (oper1, regs.byteregs[regal]);

  3239.                 break;

  3240. 

  3241.             case 0xEF:	/* EF OUT regdx eAX */

  3242.                 oper1 = regs.wordregs[regdx];

  3243.                 portout16 (oper1, regs.wordregs[regax]);

  3244.                 break;

  3245. 

  3246.             case 0xF0:	/* F0 LOCK */

  3247.                 break;

  3248. 

  3249.             case 0xF4:	/* F4 HLT */

  3250.                 hltstate = 1;

  3251.                 break;

  3252. 

  3253.             case 0xF5:	/* F5 CMC */

  3254.                 if (!cf) {

  3255.                         cf = 1;

  3256.                     }

  3257.                 else {

  3258.                         cf = 0;

  3259.                     }

  3260.                 break;

  3261. 

  3262.             case 0xF6:	/* F6 GRP3a Eb */

  3263.                 modregrm();

  3264.                 oper1b = readrm8 (rm);

  3265.                 op_grp3_8();

  3266.                 if ( (reg > 1) && (reg < 4) ) {

  3267.                         writerm8 (rm, res8);

  3268.                     }

  3269.                 break;

  3270. 

  3271.             case 0xF7:	/* F7 GRP3b Ev */

  3272.                 modregrm();

  3273.                 oper1 = readrm16 (rm);

  3274.                 op_grp3_16();

  3275.                 if ( (reg > 1) && (reg < 4) ) {

  3276.                         writerm16 (rm, res16);

  3277.                     }

  3278.                 break;

  3279. 

  3280.             case 0xF8:	/* F8 CLC */

  3281.                 cf = 0;

  3282.                 break;

  3283. 

  3284.             case 0xF9:	/* F9 STC */

  3285.                 cf = 1;

  3286.                 break;

  3287. 

  3288.             case 0xFA:	/* FA CLI */

  3289.                 ifl = 0;

  3290.                 break;

  3291. 

  3292.             case 0xFB:	/* FB STI */

  3293.                 ifl = 1;

  3294.                 break;

  3295. 

  3296.             case 0xFC:	/* FC CLD */

  3297.                 df = 0;

  3298.                 break;

  3299. 

  3300.             case 0xFD:	/* FD STD */

  3301.                 df = 1;

  3302.                 break;

  3303. 

  3304.             case 0xFE:	/* FE GRP4 Eb */

  3305.                 modregrm();

  3306.                 oper1b = readrm8 (rm);

  3307.                 oper2b = 1;

  3308.                 if (!reg) {

  3309.                         tempcf = cf;

  3310.                         res8 = oper1b + oper2b;

  3311.                         flag_add8 (oper1b, oper2b);

  3312.                         cf = tempcf;

  3313.                         writerm8 (rm, res8);

  3314.                     }

  3315.                 else {

  3316.                         tempcf = cf;

  3317.                         res8 = oper1b - oper2b;

  3318.                         flag_sub8 (oper1b, oper2b);

  3319.                         cf = tempcf;

  3320.                         writerm8 (rm, res8);

  3321.                     }

  3322.                 break;

  3323. 

  3324.             case 0xFF:	/* FF GRP5 Ev */

  3325.                 modregrm();

  3326.                 oper1 = readrm16 (rm);

  3327.                 op_grp5();

  3328.                 break;

  3329. 

  3330.             default:

  3331.                 intcall86 (6); /* trip invalid opcode exception (this occurs on the 80186+, 8086/8088 CPUs treat them as NOPs. */

  3332.                                /* technically they aren't exactly like NOPs in most cases, but for our pursoses, that's accurate enough. */

  3333.                 break;

  3334.         }

  3335.     }

  3336.     return 1;

  3337. }

  3338. 

  3339. void reset86(uint16_t startip) {

  3340. 	segregs[regcs] = 0;

  3341. 	ip = startip;

  3342. 	hltstate = 0;

  3343. }