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collapseos/emul/8086/cpu.c

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  1. /* Extracted from the Fake86 project and heavily modified to run within

  2.    the Collapse OS project with its simple needs.

  3. */

  4. /*

  5.   Fake86: A portable, open-source 8086 PC emulator.

  6.   Copyright (C)2010-2013 Mike Chambers

  7. 

  8.   This program is free software; you can redistribute it and/or

  9.   modify it under the terms of the GNU General Public License

  10.   as published by the Free Software Foundation; either version 2

  11.   of the License, or (at your option) any later version.

  12. 

  13.   This program is distributed in the hope that it will be useful,

  14.   but WITHOUT ANY WARRANTY; without even the implied warranty of

  15.   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

  16.   GNU General Public License for more details.

  17. 

  18.   You should have received a copy of the GNU General Public License

  19.   along with this program; if not, write to the Free Software

  20.   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.

  21. */

  22. 

  23. #include <stdint.h>

  24. #include <stdio.h>

  25. #include "cpu.h"

  26. 

  27. // Defines below are from config.h

  28. //be sure to only define ONE of the CPU_* options at any given time, or

  29. //you will likely get some unexpected/bad results!

  30. //#define CPU_8086

  31. //#define CPU_186

  32. #define CPU_V20

  33. //#define CPU_286

  34. 

  35. #if defined(CPU_8086)

  36. 	#define CPU_CLEAR_ZF_ON_MUL

  37. 	#define CPU_ALLOW_POP_CS

  38. #else

  39. 	#define CPU_ALLOW_ILLEGAL_OP_EXCEPTION

  40. 	#define CPU_LIMIT_SHIFT_COUNT

  41. #endif

  42. 

  43. #if defined(CPU_V20)

  44. 	#define CPU_NO_SALC

  45. #endif

  46. 

  47. #if defined(CPU_286) || defined(CPU_386)

  48. 	#define CPU_286_STYLE_PUSH_SP

  49. #else

  50. 	#define CPU_SET_HIGH_FLAGS

  51. #endif

  52. 

  53. #define StepIP(x)	ip += x

  54. #define signext(value)	(int16_t)(int8_t)(value)

  55. #define signext32(value)	(int32_t)(int16_t)(value)

  56. #define getsegreg(regid)	segregs[regid]

  57. #define putsegreg(regid, writeval)	segregs[regid] = writeval

  58. 

  59. #define makeflagsword() \

  60. 	( \

  61. 	2 | (uint16_t) cf | ((uint16_t) pf << 2) | ((uint16_t) af << 4) | ((uint16_t) zf << 6) | ((uint16_t) sf << 7) | \

  62. 	((uint16_t) tf << 8) | ((uint16_t) ifl << 9) | ((uint16_t) df << 10) | ((uint16_t) of << 11) \

  63. 	)

  64. 

  65. #define decodeflagsword(x) { \

  66. 	temp16 = x; \

  67. 	cf = temp16 & 1; \

  68. 	pf = (temp16 >> 2) & 1; \

  69. 	af = (temp16 >> 4) & 1; \

  70. 	zf = (temp16 >> 6) & 1; \

  71. 	sf = (temp16 >> 7) & 1; \

  72. 	tf = (temp16 >> 8) & 1; \

  73. 	ifl = (temp16 >> 9) & 1; \

  74. 	df = (temp16 >> 10) & 1; \

  75. 	of = (temp16 >> 11) & 1; \

  76. 	}

  77. 

  78. #define modregrm() { \

  79. 	addrbyte = getmem8(segregs[regcs], ip); \

  80. 	StepIP(1); \

  81. 	mode = addrbyte >> 6; \

  82. 	reg = (addrbyte >> 3) & 7; \

  83. 	rm = addrbyte & 7; \

  84. 	switch(mode) \

  85. 	{ \

  86. 	case 0: \

  87. 	if(rm == 6) { \

  88. 	disp16 = getmem16(segregs[regcs], ip); \

  89. 	StepIP(2); \

  90. 	} \

  91. 	if(((rm == 2) || (rm == 3)) && !segoverride) { \

  92. 	useseg = segregs[regss]; \

  93. 	} \

  94. 	break; \

  95.  \

  96. 	case 1: \

  97. 	disp16 = signext(getmem8(segregs[regcs], ip)); \

  98. 	StepIP(1); \

  99. 	if(((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) { \

  100. 	useseg = segregs[regss]; \

  101. 	} \

  102. 	break; \

  103.  \

  104. 	case 2: \

  105. 	disp16 = getmem16(segregs[regcs], ip); \

  106. 	StepIP(2); \

  107. 	if(((rm == 2) || (rm == 3) || (rm == 6)) && !segoverride) { \

  108. 	useseg = segregs[regss]; \

  109. 	} \

  110. 	break; \

  111.  \

  112. 	default: \

  113. 	disp8 = 0; \

  114. 	disp16 = 0; \

  115. 	} \

  116. }

  117. uint8_t byteregtable[8] = { regal, regcl, regdl, regbl, regah, regch, regdh, regbh };

  118. 

  119. static const uint8_t parity[0x100] = {

  120. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  121. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  122. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  123. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  124. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,

  125. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  126. 	1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,

  127. 	0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1

  128. };

  129. 

  130. uint8_t	RAM[0x100000];

  131. INTHOOK INTHOOKS[0x100] = {0};

  132. uint8_t	opcode, segoverride, reptype, hltstate = 0;

  133. uint16_t segregs[4], savecs, saveip, ip, useseg, oldsp;

  134. uint8_t	tempcf, oldcf, cf, pf, af, zf, sf, tf, ifl, df, of, mode, reg, rm;

  135. uint16_t oper1, oper2, res16, disp16, temp16, dummy, stacksize, frametemp;

  136. uint8_t	oper1b, oper2b, res8, disp8, temp8, nestlev, addrbyte;

  137. uint32_t temp1, temp2, temp3, temp4, temp5, temp32, tempaddr32, ea;

  138. uint64_t totalexec;

  139. 

  140. union _bytewordregs_ regs;

  141. 

  142. uint8_t	portram[0x10000];

  143. 

  144. void intcall86(uint8_t intnum);

  145. 

  146. static void	portout (uint16_t portnum, uint8_t value) {}

  147. static void	portout16 (uint16_t portnum, uint16_t value) {}

  148. static uint8_t	portin (uint16_t portnum) { return 0; }

  149. static uint16_t portin16 (uint16_t portnum) { return 0; }

  150. 

  151. void write86 (uint32_t addr32, uint8_t value) {

  152. 	tempaddr32 = addr32 & 0xFFFFF;

  153.     RAM[tempaddr32] = value;

  154. }

  155. 

  156. void writew86 (uint32_t addr32, uint16_t value) {

  157. 	write86(addr32, (uint8_t) value);

  158. 	write86(addr32 + 1, (uint8_t) (value >> 8) );

  159. }

  160. 

  161. uint8_t read86 (uint32_t addr32) {

  162. 	addr32 &= 0xFFFFF;

  163. 	return (RAM[addr32]);

  164. }

  165. 

  166. uint16_t readw86 (uint32_t addr32) {

  167. 	return ( (uint16_t) read86 (addr32) | (uint16_t) (read86 (addr32 + 1) << 8) );

  168. }

  169. 

  170. static void flag_szp8 (uint8_t value) {

  171. 	if (!value) {

  172. 			zf = 1;

  173. 		}

  174. 	else {

  175. 			zf = 0;	/* set or clear zero flag */

  176. 		}

  177. 

  178. 	if (value & 0x80) {

  179. 			sf = 1;

  180. 		}

  181. 	else {

  182. 			sf = 0;	/* set or clear sign flag */

  183. 		}

  184. 

  185. 	pf = parity[value]; /* retrieve parity state from lookup table */

  186. }

  187. 

  188. static void flag_szp16 (uint16_t value) {

  189. 	if (!value) {

  190. 			zf = 1;

  191. 		}

  192. 	else {

  193. 			zf = 0;	/* set or clear zero flag */

  194. 		}

  195. 

  196. 	if (value & 0x8000) {

  197. 			sf = 1;

  198. 		}

  199. 	else {

  200. 			sf = 0;	/* set or clear sign flag */

  201. 		}

  202. 

  203. 	pf = parity[value & 255];	/* retrieve parity state from lookup table */

  204. }

  205. 

  206. static void flag_log8 (uint8_t value) {

  207. 	flag_szp8 (value);

  208. 	cf = 0;

  209. 	of = 0; /* bitwise logic ops always clear carry and overflow */

  210. }

  211. 

  212. static void flag_log16 (uint16_t value) {

  213. 	flag_szp16 (value);

  214. 	cf = 0;

  215. 	of = 0; /* bitwise logic ops always clear carry and overflow */

  216. }

  217. 

  218. static void flag_adc8 (uint8_t v1, uint8_t v2, uint8_t v3) {

  219. 

  220. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  221. 	uint16_t	dst;

  222. 

  223. 	dst = (uint16_t) v1 + (uint16_t) v2 + (uint16_t) v3;

  224. 	flag_szp8 ( (uint8_t) dst);

  225. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x80) == 0x80) {

  226. 			of = 1;

  227. 		}

  228. 	else {

  229. 			of = 0; /* set or clear overflow flag */

  230. 		}

  231. 

  232. 	if (dst & 0xFF00) {

  233. 			cf = 1;

  234. 		}

  235. 	else {

  236. 			cf = 0; /* set or clear carry flag */

  237. 		}

  238. 

  239. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  240. 			af = 1;

  241. 		}

  242. 	else {

  243. 			af = 0; /* set or clear auxilliary flag */

  244. 		}

  245. }

  246. 

  247. static void flag_adc16 (uint16_t v1, uint16_t v2, uint16_t v3) {

  248. 

  249. 	uint32_t	dst;

  250. 

  251. 	dst = (uint32_t) v1 + (uint32_t) v2 + (uint32_t) v3;

  252. 	flag_szp16 ( (uint16_t) dst);

  253. 	if ( ( ( (dst ^ v1) & (dst ^ v2) ) & 0x8000) == 0x8000) {

  254. 			of = 1;

  255. 		}

  256. 	else {

  257. 			of = 0;

  258. 		}

  259. 

  260. 	if (dst & 0xFFFF0000) {

  261. 			cf = 1;

  262. 		}

  263. 	else {

  264. 			cf = 0;

  265. 		}

  266. 

  267. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  268. 			af = 1;

  269. 		}

  270. 	else {

  271. 			af = 0;

  272. 		}

  273. }

  274. 

  275. static void flag_add8 (uint8_t v1, uint8_t v2) {

  276. 	/* v1 = destination operand, v2 = source operand */

  277. 	uint16_t	dst;

  278. 

  279. 	dst = (uint16_t) v1 + (uint16_t) v2;

  280. 	flag_szp8 ( (uint8_t) dst);

  281. 	if (dst & 0xFF00) {

  282. 			cf = 1;

  283. 		}

  284. 	else {

  285. 			cf = 0;

  286. 		}

  287. 

  288. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x80) == 0x80) {

  289. 			of = 1;

  290. 		}

  291. 	else {

  292. 			of = 0;

  293. 		}

  294. 

  295. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  296. 			af = 1;

  297. 		}

  298. 	else {

  299. 			af = 0;

  300. 		}

  301. }

  302. 

  303. static void flag_add16 (uint16_t v1, uint16_t v2) {

  304. 	/* v1 = destination operand, v2 = source operand */

  305. 	uint32_t	dst;

  306. 

  307. 	dst = (uint32_t) v1 + (uint32_t) v2;

  308. 	flag_szp16 ( (uint16_t) dst);

  309. 	if (dst & 0xFFFF0000) {

  310. 			cf = 1;

  311. 		}

  312. 	else {

  313. 			cf = 0;

  314. 		}

  315. 

  316. 	if ( ( (dst ^ v1) & (dst ^ v2) & 0x8000) == 0x8000) {

  317. 			of = 1;

  318. 		}

  319. 	else {

  320. 			of = 0;

  321. 		}

  322. 

  323. 	if ( ( (v1 ^ v2 ^ dst) & 0x10) == 0x10) {

  324. 			af = 1;

  325. 		}

  326. 	else {

  327. 			af = 0;

  328. 		}

  329. }

  330. 

  331. static void flag_sbb8 (uint8_t v1, uint8_t v2, uint8_t v3) {

  332. 

  333. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  334. 	uint16_t	dst;

  335. 

  336. 	v2 += v3;

  337. 	dst = (uint16_t) v1 - (uint16_t) v2;

  338. 	flag_szp8 ( (uint8_t) dst);

  339. 	if (dst & 0xFF00) {

  340. 			cf = 1;

  341. 		}

  342. 	else {

  343. 			cf = 0;

  344. 		}

  345. 

  346. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x80) {

  347. 			of = 1;

  348. 		}

  349. 	else {

  350. 			of = 0;

  351. 		}

  352. 

  353. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  354. 			af = 1;

  355. 		}

  356. 	else {

  357. 			af = 0;

  358. 		}

  359. }

  360. 

  361. static void flag_sbb16 (uint16_t v1, uint16_t v2, uint16_t v3) {

  362. 

  363. 	/* v1 = destination operand, v2 = source operand, v3 = carry flag */

  364. 	uint32_t	dst;

  365. 

  366. 	v2 += v3;

  367. 	dst = (uint32_t) v1 - (uint32_t) v2;

  368. 	flag_szp16 ( (uint16_t) dst);

  369. 	if (dst & 0xFFFF0000) {

  370. 			cf = 1;

  371. 		}

  372. 	else {

  373. 			cf = 0;

  374. 		}

  375. 

  376. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x8000) {

  377. 			of = 1;

  378. 		}

  379. 	else {

  380. 			of = 0;

  381. 		}

  382. 

  383. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  384. 			af = 1;

  385. 		}

  386. 	else {

  387. 			af = 0;

  388. 		}

  389. }

  390. 

  391. static void flag_sub8 (uint8_t v1, uint8_t v2) {

  392. 

  393. 	/* v1 = destination operand, v2 = source operand */

  394. 	uint16_t	dst;

  395. 

  396. 	dst = (uint16_t) v1 - (uint16_t) v2;

  397. 	flag_szp8 ( (uint8_t) dst);

  398. 	if (dst & 0xFF00) {

  399. 			cf = 1;

  400. 		}

  401. 	else {

  402. 			cf = 0;

  403. 		}

  404. 

  405. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x80) {

  406. 			of = 1;

  407. 		}

  408. 	else {

  409. 			of = 0;

  410. 		}

  411. 

  412. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  413. 			af = 1;

  414. 		}

  415. 	else {

  416. 			af = 0;

  417. 		}

  418. }

  419. 

  420. static void flag_sub16 (uint16_t v1, uint16_t v2) {

  421. 

  422. 	/* v1 = destination operand, v2 = source operand */

  423. 	uint32_t	dst;

  424. 

  425. 	dst = (uint32_t) v1 - (uint32_t) v2;

  426. 	flag_szp16 ( (uint16_t) dst);

  427. 	if (dst & 0xFFFF0000) {

  428. 			cf = 1;

  429. 		}

  430. 	else {

  431. 			cf = 0;

  432. 		}

  433. 

  434. 	if ( (dst ^ v1) & (v1 ^ v2) & 0x8000) {

  435. 			of = 1;

  436. 		}

  437. 	else {

  438. 			of = 0;

  439. 		}

  440. 

  441. 	if ( (v1 ^ v2 ^ dst) & 0x10) {

  442. 			af = 1;

  443. 		}

  444. 	else {

  445. 			af = 0;

  446. 		}

  447. }

  448. 

  449. static void op_adc8() {

  450. 	res8 = oper1b + oper2b + cf;

  451. 	flag_adc8 (oper1b, oper2b, cf);

  452. }

  453. 

  454. static void op_adc16() {

  455. 	res16 = oper1 + oper2 + cf;

  456. 	flag_adc16 (oper1, oper2, cf);

  457. }

  458. 

  459. static void op_add8() {

  460. 	res8 = oper1b + oper2b;

  461. 	flag_add8 (oper1b, oper2b);

  462. }

  463. 

  464. static void op_add16() {

  465. 	res16 = oper1 + oper2;

  466. 	flag_add16 (oper1, oper2);

  467. }

  468. 

  469. static void op_and8() {

  470. 	res8 = oper1b & oper2b;

  471. 	flag_log8 (res8);

  472. }

  473. 

  474. static void op_and16() {

  475. 	res16 = oper1 & oper2;

  476. 	flag_log16 (res16);

  477. }

  478. 

  479. static void op_or8() {

  480. 	res8 = oper1b | oper2b;

  481. 	flag_log8 (res8);

  482. }

  483. 

  484. static void op_or16() {

  485. 	res16 = oper1 | oper2;

  486. 	flag_log16 (res16);

  487. }

  488. 

  489. static void op_xor8() {

  490. 	res8 = oper1b ^ oper2b;

  491. 	flag_log8 (res8);

  492. }

  493. 

  494. static void op_xor16() {

  495. 	res16 = oper1 ^ oper2;

  496. 	flag_log16 (res16);

  497. }

  498. 

  499. static void op_sub8() {

  500. 	res8 = oper1b - oper2b;

  501. 	flag_sub8 (oper1b, oper2b);

  502. }

  503. 

  504. static void op_sub16() {

  505. 	res16 = oper1 - oper2;

  506. 	flag_sub16 (oper1, oper2);

  507. }

  508. 

  509. static void op_sbb8() {

  510. 	res8 = oper1b - (oper2b + cf);

  511. 	flag_sbb8 (oper1b, oper2b, cf);

  512. }

  513. 

  514. static void op_sbb16() {

  515. 	res16 = oper1 - (oper2 + cf);

  516. 	flag_sbb16 (oper1, oper2, cf);

  517. }

  518. 

  519. static void getea (uint8_t rmval) {

  520. 	uint32_t	tempea;

  521. 

  522. 	tempea = 0;

  523. 	switch (mode) {

  524. 			case 0:

  525. 				switch (rmval) {

  526. 						case 0:

  527. 							tempea = regs.wordregs[regbx] + regs.wordregs[regsi];

  528. 							break;

  529. 						case 1:

  530. 							tempea = regs.wordregs[regbx] + regs.wordregs[regdi];

  531. 							break;

  532. 						case 2:

  533. 							tempea = regs.wordregs[regbp] + regs.wordregs[regsi];

  534. 							break;

  535. 						case 3:

  536. 							tempea = regs.wordregs[regbp] + regs.wordregs[regdi];

  537. 							break;

  538. 						case 4:

  539. 							tempea = regs.wordregs[regsi];

  540. 							break;

  541. 						case 5:

  542. 							tempea = regs.wordregs[regdi];

  543. 							break;

  544. 						case 6:

  545. 							tempea = disp16;

  546. 							break;

  547. 						case 7:

  548. 							tempea = regs.wordregs[regbx];

  549. 							break;

  550. 					}

  551. 				break;

  552. 

  553. 			case 1:

  554. 			case 2:

  555. 				switch (rmval) {

  556. 						case 0:

  557. 							tempea = regs.wordregs[regbx] + regs.wordregs[regsi] + disp16;

  558. 							break;

  559. 						case 1:

  560. 							tempea = regs.wordregs[regbx] + regs.wordregs[regdi] + disp16;

  561. 							break;

  562. 						case 2:

  563. 							tempea = regs.wordregs[regbp] + regs.wordregs[regsi] + disp16;

  564. 							break;

  565. 						case 3:

  566. 							tempea = regs.wordregs[regbp] + regs.wordregs[regdi] + disp16;

  567. 							break;

  568. 						case 4:

  569. 							tempea = regs.wordregs[regsi] + disp16;

  570. 							break;

  571. 						case 5:

  572. 							tempea = regs.wordregs[regdi] + disp16;

  573. 							break;

  574. 						case 6:

  575. 							tempea = regs.wordregs[regbp] + disp16;

  576. 							break;

  577. 						case 7:

  578. 							tempea = regs.wordregs[regbx] + disp16;

  579. 							break;

  580. 					}

  581. 				break;

  582. 		}

  583. 

  584. 	ea = (tempea & 0xFFFF) + (useseg << 4);

  585. }

  586. 

  587. static void push (uint16_t pushval) {

  588. 	regs.wordregs[regsp] = regs.wordregs[regsp] - 2;

  589. 	putmem16 (segregs[regss], regs.wordregs[regsp], pushval);

  590. }

  591. 

  592. static uint16_t pop() {

  593. 

  594. 	uint16_t	tempval;

  595. 

  596. 	tempval = getmem16 (segregs[regss], regs.wordregs[regsp]);

  597. 	regs.wordregs[regsp] = regs.wordregs[regsp] + 2;

  598. 	return tempval;

  599. }

  600. 

  601. static uint16_t readrm16 (uint8_t rmval) {

  602. 	if (mode < 3) {

  603. 			getea (rmval);

  604. 			return read86 (ea) | ( (uint16_t) read86 (ea + 1) << 8);

  605. 		}

  606. 	else {

  607. 			return getreg16 (rmval);

  608. 		}

  609. }

  610. 

  611. static uint8_t readrm8 (uint8_t rmval) {

  612. 	if (mode < 3) {

  613. 			getea (rmval);

  614. 			return read86 (ea);

  615. 		}

  616. 	else {

  617. 			return getreg8 (rmval);

  618. 		}

  619. }

  620. 

  621. static void writerm16 (uint8_t rmval, uint16_t value) {

  622. 	if (mode < 3) {

  623. 			getea (rmval);

  624. 			write86 (ea, value & 0xFF);

  625. 			write86 (ea + 1, value >> 8);

  626. 		}

  627. 	else {

  628. 			putreg16 (rmval, value);

  629. 		}

  630. }

  631. 

  632. static void writerm8 (uint8_t rmval, uint8_t value) {

  633. 	if (mode < 3) {

  634. 			getea (rmval);

  635. 			write86 (ea, value);

  636. 		}

  637. 	else {

  638. 			putreg8 (rmval, value);

  639. 		}

  640. }

  641. 

  642. static uint8_t op_grp2_8 (uint8_t cnt) {

  643. 

  644. 	uint16_t	s;

  645. 	uint16_t	shift;

  646. 	uint16_t	oldcf;

  647. 	uint16_t	msb;

  648. 

  649. 	s = oper1b;

  650. 	oldcf = cf;

  651. #ifdef CPU_LIMIT_SHIFT_COUNT

  652. 	cnt &= 0x1F;

  653. #endif

  654. 	switch (reg) {

  655. 			case 0: /* ROL r/m8 */

  656. 				for (shift = 1; shift <= cnt; shift++) {

  657. 						if (s & 0x80) {

  658. 								cf = 1;

  659. 							}

  660. 						else {

  661. 								cf = 0;

  662. 							}

  663. 

  664. 						s = s << 1;

  665. 						s = s | cf;

  666. 					}

  667. 

  668. 				if (cnt == 1) {

  669. 						//of = cf ^ ( (s >> 7) & 1);

  670. 					if ((s & 0x80) && cf) of = 1; else of = 0;

  671. 					} else of = 0;

  672. 				break;

  673. 

  674. 			case 1: /* ROR r/m8 */

  675. 				for (shift = 1; shift <= cnt; shift++) {

  676. 						cf = s & 1;

  677. 						s = (s >> 1) | (cf << 7);

  678. 					}

  679. 

  680. 				if (cnt == 1) {

  681. 						of = (s >> 7) ^ ( (s >> 6) & 1);

  682. 					}

  683. 				break;

  684. 

  685. 			case 2: /* RCL r/m8 */

  686. 				for (shift = 1; shift <= cnt; shift++) {

  687. 						oldcf = cf;

  688. 						if (s & 0x80) {

  689. 								cf = 1;

  690. 							}

  691. 						else {

  692. 								cf = 0;

  693. 							}

  694. 

  695. 						s = s << 1;

  696. 						s = s | oldcf;

  697. 					}

  698. 

  699. 				if (cnt == 1) {

  700. 						of = cf ^ ( (s >> 7) & 1);

  701. 					}

  702. 				break;

  703. 

  704. 			case 3: /* RCR r/m8 */

  705. 				for (shift = 1; shift <= cnt; shift++) {

  706. 						oldcf = cf;

  707. 						cf = s & 1;

  708. 						s = (s >> 1) | (oldcf << 7);

  709. 					}

  710. 

  711. 				if (cnt == 1) {

  712. 						of = (s >> 7) ^ ( (s >> 6) & 1);

  713. 					}

  714. 				break;

  715. 

  716. 			case 4:

  717. 			case 6: /* SHL r/m8 */

  718. 				for (shift = 1; shift <= cnt; shift++) {

  719. 						if (s & 0x80) {

  720. 								cf = 1;

  721. 							}

  722. 						else {

  723. 								cf = 0;

  724. 							}

  725. 

  726. 						s = (s << 1) & 0xFF;

  727. 					}

  728. 

  729. 				if ( (cnt == 1) && (cf == (s >> 7) ) ) {

  730. 						of = 0;

  731. 					}

  732. 				else {

  733. 						of = 1;

  734. 					}

  735. 

  736. 				flag_szp8 ( (uint8_t) s);

  737. 				break;

  738. 

  739. 			case 5: /* SHR r/m8 */

  740. 				if ( (cnt == 1) && (s & 0x80) ) {

  741. 						of = 1;

  742. 					}

  743. 				else {

  744. 						of = 0;

  745. 					}

  746. 

  747. 				for (shift = 1; shift <= cnt; shift++) {

  748. 						cf = s & 1;

  749. 						s = s >> 1;

  750. 					}

  751. 

  752. 				flag_szp8 ( (uint8_t) s);

  753. 				break;

  754. 

  755. 			case 7: /* SAR r/m8 */

  756. 				for (shift = 1; shift <= cnt; shift++) {

  757. 						msb = s & 0x80;

  758. 						cf = s & 1;

  759. 						s = (s >> 1) | msb;

  760. 					}

  761. 

  762. 				of = 0;

  763. 				flag_szp8 ( (uint8_t) s);

  764. 				break;

  765. 		}

  766. 

  767. 	return s & 0xFF;

  768. }

  769. 

  770. static uint16_t op_grp2_16 (uint8_t cnt) {

  771. 

  772. 	uint32_t	s;

  773. 	uint32_t	shift;

  774. 	uint32_t	oldcf;

  775. 	uint32_t	msb;

  776. 

  777. 	s = oper1;

  778. 	oldcf = cf;

  779. #ifdef CPU_LIMIT_SHIFT_COUNT

  780. 	cnt &= 0x1F;

  781. #endif

  782. 	switch (reg) {

  783. 			case 0: /* ROL r/m8 */

  784. 				for (shift = 1; shift <= cnt; shift++) {

  785. 						if (s & 0x8000) {

  786. 								cf = 1;

  787. 							}

  788. 						else {

  789. 								cf = 0;

  790. 							}

  791. 

  792. 						s = s << 1;

  793. 						s = s | cf;

  794. 					}

  795. 

  796. 				if (cnt == 1) {

  797. 						of = cf ^ ( (s >> 15) & 1);

  798. 					}

  799. 				break;

  800. 

  801. 			case 1: /* ROR r/m8 */

  802. 				for (shift = 1; shift <= cnt; shift++) {

  803. 						cf = s & 1;

  804. 						s = (s >> 1) | (cf << 15);

  805. 					}

  806. 

  807. 				if (cnt == 1) {

  808. 						of = (s >> 15) ^ ( (s >> 14) & 1);

  809. 					}

  810. 				break;

  811. 

  812. 			case 2: /* RCL r/m8 */

  813. 				for (shift = 1; shift <= cnt; shift++) {

  814. 						oldcf = cf;

  815. 						if (s & 0x8000) {

  816. 								cf = 1;

  817. 							}

  818. 						else {

  819. 								cf = 0;

  820. 							}

  821. 

  822. 						s = s << 1;

  823. 						s = s | oldcf;

  824. 					}

  825. 

  826. 				if (cnt == 1) {

  827. 						of = cf ^ ( (s >> 15) & 1);

  828. 					}

  829. 				break;

  830. 

  831. 			case 3: /* RCR r/m8 */

  832. 				for (shift = 1; shift <= cnt; shift++) {

  833. 						oldcf = cf;

  834. 						cf = s & 1;

  835. 						s = (s >> 1) | (oldcf << 15);

  836. 					}

  837. 

  838. 				if (cnt == 1) {

  839. 						of = (s >> 15) ^ ( (s >> 14) & 1);

  840. 					}

  841. 				break;

  842. 

  843. 			case 4:

  844. 			case 6: /* SHL r/m8 */

  845. 				for (shift = 1; shift <= cnt; shift++) {

  846. 						if (s & 0x8000) {

  847. 								cf = 1;

  848. 							}

  849. 						else {

  850. 								cf = 0;

  851. 							}

  852. 

  853. 						s = (s << 1) & 0xFFFF;

  854. 					}

  855. 

  856. 				if ( (cnt == 1) && (cf == (s >> 15) ) ) {

  857. 						of = 0;

  858. 					}

  859. 				else {

  860. 						of = 1;

  861. 					}

  862. 

  863. 				flag_szp16 ( (uint16_t) s);

  864. 				break;

  865. 

  866. 			case 5: /* SHR r/m8 */

  867. 				if ( (cnt == 1) && (s & 0x8000) ) {

  868. 						of = 1;

  869. 					}

  870. 				else {

  871. 						of = 0;

  872. 					}

  873. 

  874. 				for (shift = 1; shift <= cnt; shift++) {

  875. 						cf = s & 1;

  876. 						s = s >> 1;

  877. 					}

  878. 

  879. 				flag_szp16 ( (uint16_t) s);

  880. 				break;

  881. 

  882. 			case 7: /* SAR r/m8 */

  883. 				for (shift = 1; shift <= cnt; shift++) {

  884. 						msb = s & 0x8000;

  885. 						cf = s & 1;

  886. 						s = (s >> 1) | msb;

  887. 					}

  888. 

  889. 				of = 0;

  890. 				flag_szp16 ( (uint16_t) s);

  891. 				break;

  892. 		}

  893. 

  894. 	return (uint16_t) s & 0xFFFF;

  895. }

  896. 

  897. static void op_div8 (uint16_t valdiv, uint8_t divisor) {

  898. 	if (divisor == 0) {

  899. 			intcall86 (0);

  900. 			return;

  901. 		}

  902. 

  903. 	if ( (valdiv / (uint16_t) divisor) > 0xFF) {

  904. 			intcall86 (0);

  905. 			return;

  906. 		}

  907. 

  908. 	regs.byteregs[regah] = valdiv % (uint16_t) divisor;

  909. 	regs.byteregs[regal] = valdiv / (uint16_t) divisor;

  910. }

  911. 

  912. static void op_idiv8 (uint16_t valdiv, uint8_t divisor) {

  913. 

  914. 	uint16_t	s1;

  915. 	uint16_t	s2;

  916. 	uint16_t	d1;

  917. 	uint16_t	d2;

  918. 	int	sign;

  919. 

  920. 	if (divisor == 0) {

  921. 			intcall86 (0);

  922. 			return;

  923. 		}

  924. 

  925. 	s1 = valdiv;

  926. 	s2 = divisor;

  927. 	sign = ( ( (s1 ^ s2) & 0x8000) != 0);

  928. 	s1 = (s1 < 0x8000) ? s1 : ( (~s1 + 1) & 0xffff);

  929. 	s2 = (s2 < 0x8000) ? s2 : ( (~s2 + 1) & 0xffff);

  930. 	d1 = s1 / s2;

  931. 	d2 = s1 % s2;

  932. 	if (d1 & 0xFF00) {

  933. 			intcall86 (0);

  934. 			return;

  935. 		}

  936. 

  937. 	if (sign) {

  938. 			d1 = (~d1 + 1) & 0xff;

  939. 			d2 = (~d2 + 1) & 0xff;

  940. 		}

  941. 

  942. 	regs.byteregs[regah] = (uint8_t) d2;

  943. 	regs.byteregs[regal] = (uint8_t) d1;

  944. }

  945. 

  946. static void op_grp3_8() {

  947. 	oper1 = signext (oper1b);

  948. 	oper2 = signext (oper2b);

  949. 	switch (reg) {

  950. 			case 0:

  951. 			case 1: /* TEST */

  952. 				flag_log8 (oper1b & getmem8 (segregs[regcs], ip) );

  953. 				StepIP (1);

  954. 				break;

  955. 

  956. 			case 2: /* NOT */

  957. 				res8 = ~oper1b;

  958. 				break;

  959. 

  960. 			case 3: /* NEG */

  961. 				res8 = (~oper1b) + 1;

  962. 				flag_sub8 (0, oper1b);

  963. 				if (res8 == 0) {

  964. 						cf = 0;

  965. 					}

  966. 				else {

  967. 						cf = 1;

  968. 					}

  969. 				break;

  970. 

  971. 			case 4: /* MUL */

  972. 				temp1 = (uint32_t) oper1b * (uint32_t) regs.byteregs[regal];

  973. 				regs.wordregs[regax] = temp1 & 0xFFFF;

  974. 				flag_szp8 ( (uint8_t) temp1);

  975. 				if (regs.byteregs[regah]) {

  976. 						cf = 1;

  977. 						of = 1;

  978. 					}

  979. 				else {

  980. 						cf = 0;

  981. 						of = 0;

  982. 					}

  983. #ifdef CPU_CLEAR_ZF_ON_MUL

  984. 				zf = 0;

  985. #endif

  986. 				break;

  987. 

  988. 			case 5: /* IMUL */

  989. 				oper1 = signext (oper1b);

  990. 				temp1 = signext (regs.byteregs[regal]);

  991. 				temp2 = oper1;

  992. 				if ( (temp1 & 0x80) == 0x80) {

  993. 						temp1 = temp1 | 0xFFFFFF00;

  994. 					}

  995. 

  996. 				if ( (temp2 & 0x80) == 0x80) {

  997. 						temp2 = temp2 | 0xFFFFFF00;

  998. 					}

  999. 

  1000. 				temp3 = (temp1 * temp2) & 0xFFFF;

  1001. 				regs.wordregs[regax] = temp3 & 0xFFFF;

  1002. 				if (regs.byteregs[regah]) {

  1003. 						cf = 1;

  1004. 						of = 1;

  1005. 					}

  1006. 				else {

  1007. 						cf = 0;

  1008. 						of = 0;

  1009. 					}

  1010. #ifdef CPU_CLEAR_ZF_ON_MUL

  1011. 				zf = 0;

  1012. #endif

  1013. 				break;

  1014. 

  1015. 			case 6: /* DIV */

  1016. 				op_div8 (regs.wordregs[regax], oper1b);

  1017. 				break;

  1018. 

  1019. 			case 7: /* IDIV */

  1020. 				op_idiv8 (regs.wordregs[regax], oper1b);

  1021. 				break;

  1022. 		}

  1023. }

  1024. 

  1025. static void op_div16 (uint32_t valdiv, uint16_t divisor) {

  1026. 	if (divisor == 0) {

  1027. 			intcall86 (0);

  1028. 			return;

  1029. 		}

  1030. 

  1031. 	if ( (valdiv / (uint32_t) divisor) > 0xFFFF) {

  1032. 			intcall86 (0);

  1033. 			return;

  1034. 		}

  1035. 

  1036. 	regs.wordregs[regdx] = valdiv % (uint32_t) divisor;

  1037. 	regs.wordregs[regax] = valdiv / (uint32_t) divisor;

  1038. }

  1039. 

  1040. static void op_idiv16 (uint32_t valdiv, uint16_t divisor) {

  1041. 

  1042. 	uint32_t	d1;

  1043. 	uint32_t	d2;

  1044. 	uint32_t	s1;

  1045. 	uint32_t	s2;

  1046. 	int	sign;

  1047. 

  1048. 	if (divisor == 0) {

  1049. 			intcall86 (0);

  1050. 			return;

  1051. 		}

  1052. 

  1053. 	s1 = valdiv;

  1054. 	s2 = divisor;

  1055. 	s2 = (s2 & 0x8000) ? (s2 | 0xffff0000) : s2;

  1056. 	sign = ( ( (s1 ^ s2) & 0x80000000) != 0);

  1057. 	s1 = (s1 < 0x80000000) ? s1 : ( (~s1 + 1) & 0xffffffff);

  1058. 	s2 = (s2 < 0x80000000) ? s2 : ( (~s2 + 1) & 0xffffffff);

  1059. 	d1 = s1 / s2;

  1060. 	d2 = s1 % s2;

  1061. 	if (d1 & 0xFFFF0000) {

  1062. 			intcall86 (0);

  1063. 			return;

  1064. 		}

  1065. 

  1066. 	if (sign) {

  1067. 			d1 = (~d1 + 1) & 0xffff;

  1068. 			d2 = (~d2 + 1) & 0xffff;

  1069. 		}

  1070. 

  1071. 	regs.wordregs[regax] = d1;

  1072. 	regs.wordregs[regdx] = d2;

  1073. }

  1074. 

  1075. static void op_grp3_16() {

  1076. 	switch (reg) {

  1077. 			case 0:

  1078. 			case 1: /* TEST */

  1079. 				flag_log16 (oper1 & getmem16 (segregs[regcs], ip) );

  1080. 				StepIP (2);

  1081. 				break;

  1082. 

  1083. 			case 2: /* NOT */

  1084. 				res16 = ~oper1;

  1085. 				break;

  1086. 

  1087. 			case 3: /* NEG */

  1088. 				res16 = (~oper1) + 1;

  1089. 				flag_sub16 (0, oper1);

  1090. 				if (res16) {

  1091. 						cf = 1;

  1092. 					}

  1093. 				else {

  1094. 						cf = 0;

  1095. 					}

  1096. 				break;

  1097. 

  1098. 			case 4: /* MUL */

  1099. 				temp1 = (uint32_t) oper1 * (uint32_t) regs.wordregs[regax];

  1100. 				regs.wordregs[regax] = temp1 & 0xFFFF;

  1101. 				regs.wordregs[regdx] = temp1 >> 16;

  1102. 				flag_szp16 ( (uint16_t) temp1);

  1103. 				if (regs.wordregs[regdx]) {

  1104. 						cf = 1;

  1105. 						of = 1;

  1106. 					}

  1107. 				else {

  1108. 						cf = 0;

  1109. 						of = 0;

  1110. 					}

  1111. #ifdef CPU_CLEAR_ZF_ON_MUL

  1112. 				zf = 0;

  1113. #endif

  1114. 				break;

  1115. 

  1116. 			case 5: /* IMUL */

  1117. 				temp1 = regs.wordregs[regax];

  1118. 				temp2 = oper1;

  1119. 				if (temp1 & 0x8000) {

  1120. 						temp1 |= 0xFFFF0000;

  1121. 					}

  1122. 

  1123. 				if (temp2 & 0x8000) {

  1124. 						temp2 |= 0xFFFF0000;

  1125. 					}

  1126. 

  1127. 				temp3 = temp1 * temp2;

  1128. 				regs.wordregs[regax] = temp3 & 0xFFFF;	/* into register ax */

  1129. 				regs.wordregs[regdx] = temp3 >> 16;	/* into register dx */

  1130. 				if (regs.wordregs[regdx]) {

  1131. 						cf = 1;

  1132. 						of = 1;

  1133. 					}

  1134. 				else {

  1135. 						cf = 0;

  1136. 						of = 0;

  1137. 					}

  1138. #ifdef CPU_CLEAR_ZF_ON_MUL

  1139. 				zf = 0;

  1140. #endif

  1141. 				break;

  1142. 

  1143. 			case 6: /* DIV */

  1144. 				op_div16 ( ( (uint32_t) regs.wordregs[regdx] << 16) + regs.wordregs[regax], oper1);

  1145. 				break;

  1146. 

  1147. 			case 7: /* DIV */

  1148. 				op_idiv16 ( ( (uint32_t) regs.wordregs[regdx] << 16) + regs.wordregs[regax], oper1);

  1149. 				break;

  1150. 		}

  1151. }

  1152. 

  1153. static void op_grp5() {

  1154. 	switch (reg) {

  1155. 			case 0: /* INC Ev */

  1156. 				oper2 = 1;

  1157. 				tempcf = cf;

  1158. 				op_add16();

  1159. 				cf = tempcf;

  1160. 				writerm16 (rm, res16);

  1161. 				break;

  1162. 

  1163. 			case 1: /* DEC Ev */

  1164. 				oper2 = 1;

  1165. 				tempcf = cf;

  1166. 				op_sub16();

  1167. 				cf = tempcf;

  1168. 				writerm16 (rm, res16);

  1169. 				break;

  1170. 

  1171. 			case 2: /* CALL Ev */

  1172. 				push (ip);

  1173. 				ip = oper1;

  1174. 				break;

  1175. 

  1176. 			case 3: /* CALL Mp */

  1177. 				push (segregs[regcs]);

  1178. 				push (ip);

  1179. 				getea (rm);

  1180. 				ip = (uint16_t) read86 (ea) + (uint16_t) read86 (ea + 1) * 256;

  1181. 				segregs[regcs] = (uint16_t) read86 (ea + 2) + (uint16_t) read86 (ea + 3) * 256;

  1182. 				break;

  1183. 

  1184. 			case 4: /* JMP Ev */

  1185. 				ip = oper1;

  1186. 				break;

  1187. 

  1188. 			case 5: /* JMP Mp */

  1189. 				getea (rm);

  1190. 				ip = (uint16_t) read86 (ea) + (uint16_t) read86 (ea + 1) * 256;

  1191. 				segregs[regcs] = (uint16_t) read86 (ea + 2) + (uint16_t) read86 (ea + 3) * 256;

  1192. 				break;

  1193. 

  1194. 			case 6: /* PUSH Ev */

  1195. 				push (oper1);

  1196. 				break;

  1197. 		}

  1198. }

  1199. 

  1200. void intcall86(uint8_t intnum) {

  1201.     if (intnum == 0) {

  1202.         fprintf(stderr, "INT 0 called, halting\n");

  1203.         hltstate = 1;

  1204.         return;

  1205.     }

  1206.     if (INTHOOKS[intnum] != NULL) {

  1207.         INTHOOKS[intnum]();

  1208.         return;

  1209.     }

  1210.     fprintf(stderr, "Unknown INT called: %x\n", intnum);

  1211. 	/*push (makeflagsword() );

  1212. 	push (segregs[regcs]);

  1213. 	push (ip);

  1214. 	segregs[regcs] = getmem16 (0, (uint16_t) intnum * 4 + 2);

  1215. 	ip = getmem16 (0, (uint16_t) intnum * 4);

  1216. 	ifl = 0;

  1217. 	tf = 0;*/

  1218. }

  1219. 

  1220. void exec86(int execloops) {

  1221. 	int loopcount;

  1222. 	uint8_t docontinue;

  1223. 	static uint16_t firstip;

  1224. 

  1225. 	for (loopcount = 0; loopcount < execloops; loopcount++) {

  1226.         if (hltstate) return;

  1227. 

  1228.         reptype = 0;

  1229.         segoverride = 0;

  1230.         useseg = segregs[regds];

  1231.         docontinue = 0;

  1232.         firstip = ip;

  1233. 

  1234.         while (!docontinue) {

  1235.             segregs[regcs] = segregs[regcs] & 0xFFFF;

  1236.             ip = ip & 0xFFFF;

  1237.             savecs = segregs[regcs];

  1238.             saveip = ip;

  1239.             opcode = getmem8 (segregs[regcs], ip);

  1240.             StepIP (1);

  1241. 

  1242.             switch (opcode) {

  1243.                         /* segment prefix check */

  1244.                     case 0x2E:	/* segment segregs[regcs] */

  1245.                         useseg = segregs[regcs];

  1246.                         segoverride = 1;

  1247.                         break;

  1248. 

  1249.                     case 0x3E:	/* segment segregs[regds] */

  1250.                         useseg = segregs[regds];

  1251.                         segoverride = 1;

  1252.                         break;

  1253. 

  1254.                     case 0x26:	/* segment segregs[reges] */

  1255.                         useseg = segregs[reges];

  1256.                         segoverride = 1;

  1257.                         break;

  1258. 

  1259.                     case 0x36:	/* segment segregs[regss] */

  1260.                         useseg = segregs[regss];

  1261.                         segoverride = 1;

  1262.                         break;

  1263. 

  1264.                         /* repetition prefix check */

  1265.                     case 0xF3:	/* REP/REPE/REPZ */

  1266.                         reptype = 1;

  1267.                         break;

  1268. 

  1269.                     case 0xF2:	/* REPNE/REPNZ */

  1270.                         reptype = 2;

  1271.                         break;

  1272. 

  1273.                     default:

  1274.                         docontinue = 1;

  1275.                         break;

  1276.                 }

  1277.         }

  1278. 

  1279.         totalexec++;

  1280. 

  1281.         switch (opcode) {

  1282.             case 0x0:	/* 00 ADD Eb Gb */

  1283.                 modregrm();

  1284.                 oper1b = readrm8 (rm);

  1285.                 oper2b = getreg8 (reg);

  1286.                 op_add8();

  1287.                 writerm8 (rm, res8);

  1288.                 break;

  1289. 

  1290.             case 0x1:	/* 01 ADD Ev Gv */

  1291.                 modregrm();

  1292.                 oper1 = readrm16 (rm);

  1293.                 oper2 = getreg16 (reg);

  1294.                 op_add16();

  1295.                 writerm16 (rm, res16);

  1296.                 break;

  1297. 

  1298.             case 0x2:	/* 02 ADD Gb Eb */

  1299.                 modregrm();

  1300.                 oper1b = getreg8 (reg);

  1301.                 oper2b = readrm8 (rm);

  1302.                 op_add8();

  1303.                 putreg8 (reg, res8);

  1304.                 break;

  1305. 

  1306.             case 0x3:	/* 03 ADD Gv Ev */

  1307.                 modregrm();

  1308.                 oper1 = getreg16 (reg);

  1309.                 oper2 = readrm16 (rm);

  1310.                 op_add16();

  1311.                 putreg16 (reg, res16);

  1312.                 break;

  1313. 

  1314.             case 0x4:	/* 04 ADD regs.byteregs[regal] Ib */

  1315.                 oper1b = regs.byteregs[regal];

  1316.                 oper2b = getmem8 (segregs[regcs], ip);

  1317.                 StepIP (1);

  1318.                 op_add8();

  1319.                 regs.byteregs[regal] = res8;

  1320.                 break;

  1321. 

  1322.             case 0x5:	/* 05 ADD eAX Iv */

  1323.                 oper1 = regs.wordregs[regax];

  1324.                 oper2 = getmem16 (segregs[regcs], ip);

  1325.                 StepIP (2);

  1326.                 op_add16();

  1327.                 regs.wordregs[regax] = res16;

  1328.                 break;

  1329. 

  1330.             case 0x6:	/* 06 PUSH segregs[reges] */

  1331.                 push (segregs[reges]);

  1332.                 break;

  1333. 

  1334.             case 0x7:	/* 07 POP segregs[reges] */

  1335.                 segregs[reges] = pop();

  1336.                 break;

  1337. 

  1338.             case 0x8:	/* 08 OR Eb Gb */

  1339.                 modregrm();

  1340.                 oper1b = readrm8 (rm);

  1341.                 oper2b = getreg8 (reg);

  1342.                 op_or8();

  1343.                 writerm8 (rm, res8);

  1344.                 break;

  1345. 

  1346.             case 0x9:	/* 09 OR Ev Gv */

  1347.                 modregrm();

  1348.                 oper1 = readrm16 (rm);

  1349.                 oper2 = getreg16 (reg);

  1350.                 op_or16();

  1351.                 writerm16 (rm, res16);

  1352.                 break;

  1353. 

  1354.             case 0xA:	/* 0A OR Gb Eb */

  1355.                 modregrm();

  1356.                 oper1b = getreg8 (reg);

  1357.                 oper2b = readrm8 (rm);

  1358.                 op_or8();

  1359.                 putreg8 (reg, res8);

  1360.                 break;

  1361. 

  1362.             case 0xB:	/* 0B OR Gv Ev */

  1363.                 modregrm();

  1364.                 oper1 = getreg16 (reg);

  1365.                 oper2 = readrm16 (rm);

  1366.                 op_or16();

  1367.                 if ( (oper1 == 0xF802) && (oper2 == 0xF802) ) {

  1368.                         sf = 0;	/* cheap hack to make Wolf 3D think we're a 286 so it plays */

  1369.                     }

  1370. 

  1371.                 putreg16 (reg, res16);

  1372.                 break;

  1373. 

  1374.             case 0xC:	/* 0C OR regs.byteregs[regal] Ib */

  1375.                 oper1b = regs.byteregs[regal];

  1376.                 oper2b = getmem8 (segregs[regcs], ip);

  1377.                 StepIP (1);

  1378.                 op_or8();

  1379.                 regs.byteregs[regal] = res8;

  1380.                 break;

  1381. 

  1382.             case 0xD:	/* 0D OR eAX Iv */

  1383.                 oper1 = regs.wordregs[regax];

  1384.                 oper2 = getmem16 (segregs[regcs], ip);

  1385.                 StepIP (2);

  1386.                 op_or16();

  1387.                 regs.wordregs[regax] = res16;

  1388.                 break;

  1389. 

  1390.             case 0xE:	/* 0E PUSH segregs[regcs] */

  1391.                 push (segregs[regcs]);

  1392.                 break;

  1393. 

  1394. #ifdef CPU_ALLOW_POP_CS //only the 8086/8088 does this.

  1395.             case 0xF: //0F POP CS

  1396.                 segregs[regcs] = pop();

  1397.                 break;

  1398. #endif

  1399. 

  1400.             case 0x10:	/* 10 ADC Eb Gb */

  1401.                 modregrm();

  1402.                 oper1b = readrm8 (rm);

  1403.                 oper2b = getreg8 (reg);

  1404.                 op_adc8();

  1405.                 writerm8 (rm, res8);

  1406.                 break;

  1407. 

  1408.             case 0x11:	/* 11 ADC Ev Gv */

  1409.                 modregrm();

  1410.                 oper1 = readrm16 (rm);

  1411.                 oper2 = getreg16 (reg);

  1412.                 op_adc16();

  1413.                 writerm16 (rm, res16);

  1414.                 break;

  1415. 

  1416.             case 0x12:	/* 12 ADC Gb Eb */

  1417.                 modregrm();

  1418.                 oper1b = getreg8 (reg);

  1419.                 oper2b = readrm8 (rm);

  1420.                 op_adc8();

  1421.                 putreg8 (reg, res8);

  1422.                 break;

  1423. 

  1424.             case 0x13:	/* 13 ADC Gv Ev */

  1425.                 modregrm();

  1426.                 oper1 = getreg16 (reg);

  1427.                 oper2 = readrm16 (rm);

  1428.                 op_adc16();

  1429.                 putreg16 (reg, res16);

  1430.                 break;

  1431. 

  1432.             case 0x14:	/* 14 ADC regs.byteregs[regal] Ib */

  1433.                 oper1b = regs.byteregs[regal];

  1434.                 oper2b = getmem8 (segregs[regcs], ip);

  1435.                 StepIP (1);

  1436.                 op_adc8();

  1437.                 regs.byteregs[regal] = res8;

  1438.                 break;

  1439. 

  1440.             case 0x15:	/* 15 ADC eAX Iv */

  1441.                 oper1 = regs.wordregs[regax];

  1442.                 oper2 = getmem16 (segregs[regcs], ip);

  1443.                 StepIP (2);

  1444.                 op_adc16();

  1445.                 regs.wordregs[regax] = res16;

  1446.                 break;

  1447. 

  1448.             case 0x16:	/* 16 PUSH segregs[regss] */

  1449.                 push (segregs[regss]);

  1450.                 break;

  1451. 

  1452.             case 0x17:	/* 17 POP segregs[regss] */

  1453.                 segregs[regss] = pop();

  1454.                 break;

  1455. 

  1456.             case 0x18:	/* 18 SBB Eb Gb */

  1457.                 modregrm();

  1458.                 oper1b = readrm8 (rm);

  1459.                 oper2b = getreg8 (reg);

  1460.                 op_sbb8();

  1461.                 writerm8 (rm, res8);

  1462.                 break;

  1463. 

  1464.             case 0x19:	/* 19 SBB Ev Gv */

  1465.                 modregrm();

  1466.                 oper1 = readrm16 (rm);

  1467.                 oper2 = getreg16 (reg);

  1468.                 op_sbb16();

  1469.                 writerm16 (rm, res16);

  1470.                 break;

  1471. 

  1472.             case 0x1A:	/* 1A SBB Gb Eb */

  1473.                 modregrm();

  1474.                 oper1b = getreg8 (reg);

  1475.                 oper2b = readrm8 (rm);

  1476.                 op_sbb8();

  1477.                 putreg8 (reg, res8);

  1478.                 break;

  1479. 

  1480.             case 0x1B:	/* 1B SBB Gv Ev */

  1481.                 modregrm();

  1482.                 oper1 = getreg16 (reg);

  1483.                 oper2 = readrm16 (rm);

  1484.                 op_sbb16();

  1485.                 putreg16 (reg, res16);

  1486.                 break;

  1487. 

  1488.             case 0x1C:	/* 1C SBB regs.byteregs[regal] Ib */

  1489.                 oper1b = regs.byteregs[regal];

  1490.                 oper2b = getmem8 (segregs[regcs], ip);

  1491.                 StepIP (1);

  1492.                 op_sbb8();

  1493.                 regs.byteregs[regal] = res8;

  1494.                 break;

  1495. 

  1496.             case 0x1D:	/* 1D SBB eAX Iv */

  1497.                 oper1 = regs.wordregs[regax];

  1498.                 oper2 = getmem16 (segregs[regcs], ip);

  1499.                 StepIP (2);

  1500.                 op_sbb16();

  1501.                 regs.wordregs[regax] = res16;

  1502.                 break;

  1503. 

  1504.             case 0x1E:	/* 1E PUSH segregs[regds] */

  1505.                 push (segregs[regds]);

  1506.                 break;

  1507. 

  1508.             case 0x1F:	/* 1F POP segregs[regds] */

  1509.                 segregs[regds] = pop();

  1510.                 break;

  1511. 

  1512.             case 0x20:	/* 20 AND Eb Gb */

  1513.                 modregrm();

  1514.                 oper1b = readrm8 (rm);

  1515.                 oper2b = getreg8 (reg);

  1516.                 op_and8();

  1517.                 writerm8 (rm, res8);

  1518.                 break;

  1519. 

  1520.             case 0x21:	/* 21 AND Ev Gv */

  1521.                 modregrm();

  1522.                 oper1 = readrm16 (rm);

  1523.                 oper2 = getreg16 (reg);

  1524.                 op_and16();

  1525.                 writerm16 (rm, res16);

  1526.                 break;

  1527. 

  1528.             case 0x22:	/* 22 AND Gb Eb */

  1529.                 modregrm();

  1530.                 oper1b = getreg8 (reg);

  1531.                 oper2b = readrm8 (rm);

  1532.                 op_and8();

  1533.                 putreg8 (reg, res8);

  1534.                 break;

  1535. 

  1536.             case 0x23:	/* 23 AND Gv Ev */

  1537.                 modregrm();

  1538.                 oper1 = getreg16 (reg);

  1539.                 oper2 = readrm16 (rm);

  1540.                 op_and16();

  1541.                 putreg16 (reg, res16);

  1542.                 break;

  1543. 

  1544.             case 0x24:	/* 24 AND regs.byteregs[regal] Ib */

  1545.                 oper1b = regs.byteregs[regal];

  1546.                 oper2b = getmem8 (segregs[regcs], ip);

  1547.                 StepIP (1);

  1548.                 op_and8();

  1549.                 regs.byteregs[regal] = res8;

  1550.                 break;

  1551. 

  1552.             case 0x25:	/* 25 AND eAX Iv */

  1553.                 oper1 = regs.wordregs[regax];

  1554.                 oper2 = getmem16 (segregs[regcs], ip);

  1555.                 StepIP (2);

  1556.                 op_and16();

  1557.                 regs.wordregs[regax] = res16;

  1558.                 break;

  1559. 

  1560.             case 0x27:	/* 27 DAA */

  1561.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1562.                         oper1 = regs.byteregs[regal] + 6;

  1563.                         regs.byteregs[regal] = oper1 & 255;

  1564.                         if (oper1 & 0xFF00) {

  1565.                                 cf = 1;

  1566.                             }

  1567.                         else {

  1568.                                 cf = 0;

  1569.                             }

  1570. 

  1571.                         af = 1;

  1572.                     }

  1573.                 else {

  1574.                         //af = 0;

  1575.                     }

  1576. 

  1577.                 if ( (regs.byteregs[regal]  > 0x9F) || (cf == 1) ) {

  1578.                         regs.byteregs[regal] = regs.byteregs[regal] + 0x60;

  1579.                         cf = 1;

  1580.                     }

  1581.                 else {

  1582.                         //cf = 0;

  1583.                     }

  1584. 

  1585.                 regs.byteregs[regal] = regs.byteregs[regal] & 255;

  1586.                 flag_szp8 (regs.byteregs[regal]);

  1587.                 break;

  1588. 

  1589.             case 0x28:	/* 28 SUB Eb Gb */

  1590.                 modregrm();

  1591.                 oper1b = readrm8 (rm);

  1592.                 oper2b = getreg8 (reg);

  1593.                 op_sub8();

  1594.                 writerm8 (rm, res8);

  1595.                 break;

  1596. 

  1597.             case 0x29:	/* 29 SUB Ev Gv */

  1598.                 modregrm();

  1599.                 oper1 = readrm16 (rm);

  1600.                 oper2 = getreg16 (reg);

  1601.                 op_sub16();

  1602.                 writerm16 (rm, res16);

  1603.                 break;

  1604. 

  1605.             case 0x2A:	/* 2A SUB Gb Eb */

  1606.                 modregrm();

  1607.                 oper1b = getreg8 (reg);

  1608.                 oper2b = readrm8 (rm);

  1609.                 op_sub8();

  1610.                 putreg8 (reg, res8);

  1611.                 break;

  1612. 

  1613.             case 0x2B:	/* 2B SUB Gv Ev */

  1614.                 modregrm();

  1615.                 oper1 = getreg16 (reg);

  1616.                 oper2 = readrm16 (rm);

  1617.                 op_sub16();

  1618.                 putreg16 (reg, res16);

  1619.                 break;

  1620. 

  1621.             case 0x2C:	/* 2C SUB regs.byteregs[regal] Ib */

  1622.                 oper1b = regs.byteregs[regal];

  1623.                 oper2b = getmem8 (segregs[regcs], ip);

  1624.                 StepIP (1);

  1625.                 op_sub8();

  1626.                 regs.byteregs[regal] = res8;

  1627.                 break;

  1628. 

  1629.             case 0x2D:	/* 2D SUB eAX Iv */

  1630.                 oper1 = regs.wordregs[regax];

  1631.                 oper2 = getmem16 (segregs[regcs], ip);

  1632.                 StepIP (2);

  1633.                 op_sub16();

  1634.                 regs.wordregs[regax] = res16;

  1635.                 break;

  1636. 

  1637.             case 0x2F:	/* 2F DAS */

  1638.                 if ( ( (regs.byteregs[regal] & 15) > 9) || (af == 1) ) {

  1639.                         oper1 = regs.byteregs[regal] - 6;

  1640.                         regs.byteregs[regal] = oper1 & 255;

  1641.                         if (oper1 & 0xFF00) {

  1642.                                 cf = 1;

  1643.                             }

  1644.                         else {

  1645.                                 cf = 0;

  1646.                             }

  1647. 

  1648.                         af = 1;

  1649.                     }

  1650.                 else {

  1651.                         af = 0;

  1652.                     }

  1653. 

  1654.                 if ( ( (regs.byteregs[regal] & 0xF0) > 0x90) || (cf == 1) ) {

  1655.                         regs.byteregs[regal] = regs.byteregs[regal] - 0x60;

  1656.                         cf = 1;

  1657.                     }

  1658.                 else {

  1659.                         cf = 0;

  1660.                     }

  1661. 

  1662.                 flag_szp8 (regs.byteregs[regal]);

  1663.                 break;

  1664. 

  1665.             case 0x30:	/* 30 XOR Eb Gb */

  1666.                 modregrm();

  1667.                 oper1b = readrm8 (rm);

  1668.                 oper2b = getreg8 (reg);

  1669.                 op_xor8();

  1670.                 writerm8 (rm, res8);

  1671.                 break;

  1672. 

  1673.             case 0x31:	/* 31 XOR Ev Gv */

  1674.                 modregrm();

  1675.                 oper1 = readrm16 (rm);

  1676.                 oper2 = getreg16 (reg);

  1677.                 op_xor16();

  1678.                 writerm16 (rm, res16);

  1679.                 break;

  1680. 

  1681.             case 0x32:	/* 32 XOR Gb Eb */

  1682.                 modregrm();

  1683.                 oper1b = getreg8 (reg);

  1684.                 oper2b = readrm8 (rm);

  1685.                 op_xor8();

  1686.                 putreg8 (reg, res8);

  1687.                 break;

  1688. 

  1689.             case 0x33:	/* 33 XOR Gv Ev */

  1690.                 modregrm();

  1691.                 oper1 = getreg16 (reg);

  1692.                 oper2 = readrm16 (rm);

  1693.                 op_xor16();

  1694.                 putreg16 (reg, res16);

  1695.                 break;

  1696. 

  1697.             case 0x34:	/* 34 XOR regs.byteregs[regal] Ib */

  1698.                 oper1b = regs.byteregs[regal];

  1699.                 oper2b = getmem8 (segregs[regcs], ip);

  1700.                 StepIP (1);

  1701.                 op_xor8();

  1702.                 regs.byteregs[regal] = res8;

  1703.                 break;

  1704. 

  1705.             case 0x35:	/* 35 XOR eAX Iv */

  1706.                 oper1 = regs.wordregs[regax];

  1707.                 oper2 = getmem16 (segregs[regcs], ip);

  1708.                 StepIP (2);

  1709.                 op_xor16();

  1710.                 regs.wordregs[regax] = res16;

  1711.                 break;

  1712. 

  1713.             case 0x37:	/* 37 AAA ASCII */

  1714.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1715.                         regs.byteregs[regal] = regs.byteregs[regal] + 6;

  1716.                         regs.byteregs[regah] = regs.byteregs[regah] + 1;

  1717.                         af = 1;

  1718.                         cf = 1;

  1719.                     }

  1720.                 else {

  1721.                         af = 0;

  1722.                         cf = 0;

  1723.                     }

  1724. 

  1725.                 regs.byteregs[regal] = regs.byteregs[regal] & 0xF;

  1726.                 break;

  1727. 

  1728.             case 0x38:	/* 38 CMP Eb Gb */

  1729.                 modregrm();

  1730.                 oper1b = readrm8 (rm);

  1731.                 oper2b = getreg8 (reg);

  1732.                 flag_sub8 (oper1b, oper2b);

  1733.                 break;

  1734. 

  1735.             case 0x39:	/* 39 CMP Ev Gv */

  1736.                 modregrm();

  1737.                 oper1 = readrm16 (rm);

  1738.                 oper2 = getreg16 (reg);

  1739.                 flag_sub16 (oper1, oper2);

  1740.                 break;

  1741. 

  1742.             case 0x3A:	/* 3A CMP Gb Eb */

  1743.                 modregrm();

  1744.                 oper1b = getreg8 (reg);

  1745.                 oper2b = readrm8 (rm);

  1746.                 flag_sub8 (oper1b, oper2b);

  1747.                 break;

  1748. 

  1749.             case 0x3B:	/* 3B CMP Gv Ev */

  1750.                 modregrm();

  1751.                 oper1 = getreg16 (reg);

  1752.                 oper2 = readrm16 (rm);

  1753.                 flag_sub16 (oper1, oper2);

  1754.                 break;

  1755. 

  1756.             case 0x3C:	/* 3C CMP regs.byteregs[regal] Ib */

  1757.                 oper1b = regs.byteregs[regal];

  1758.                 oper2b = getmem8 (segregs[regcs], ip);

  1759.                 StepIP (1);

  1760.                 flag_sub8 (oper1b, oper2b);

  1761.                 break;

  1762. 

  1763.             case 0x3D:	/* 3D CMP eAX Iv */

  1764.                 oper1 = regs.wordregs[regax];

  1765.                 oper2 = getmem16 (segregs[regcs], ip);

  1766.                 StepIP (2);

  1767.                 flag_sub16 (oper1, oper2);

  1768.                 break;

  1769. 

  1770.             case 0x3F:	/* 3F AAS ASCII */

  1771.                 if ( ( (regs.byteregs[regal] & 0xF) > 9) || (af == 1) ) {

  1772.                         regs.byteregs[regal] = regs.byteregs[regal] - 6;

  1773.                         regs.byteregs[regah] = regs.byteregs[regah] - 1;

  1774.                         af = 1;

  1775.                         cf = 1;

  1776.                     }

  1777.                 else {

  1778.                         af = 0;

  1779.                         cf = 0;

  1780.                     }

  1781. 

  1782.                 regs.byteregs[regal] = regs.byteregs[regal] & 0xF;

  1783.                 break;

  1784. 

  1785.             case 0x40:	/* 40 INC eAX */

  1786.                 oldcf = cf;

  1787.                 oper1 = regs.wordregs[regax];

  1788.                 oper2 = 1;

  1789.                 op_add16();

  1790.                 cf = oldcf;

  1791.                 regs.wordregs[regax] = res16;

  1792.                 break;

  1793. 

  1794.             case 0x41:	/* 41 INC eCX */

  1795.                 oldcf = cf;

  1796.                 oper1 = regs.wordregs[regcx];

  1797.                 oper2 = 1;

  1798.                 op_add16();

  1799.                 cf = oldcf;

  1800.                 regs.wordregs[regcx] = res16;

  1801.                 break;

  1802. 

  1803.             case 0x42:	/* 42 INC eDX */

  1804.                 oldcf = cf;

  1805.                 oper1 = regs.wordregs[regdx];

  1806.                 oper2 = 1;

  1807.                 op_add16();

  1808.                 cf = oldcf;

  1809.                 regs.wordregs[regdx] = res16;

  1810.                 break;

  1811. 

  1812.             case 0x43:	/* 43 INC eBX */

  1813.                 oldcf = cf;

  1814.                 oper1 = regs.wordregs[regbx];

  1815.                 oper2 = 1;

  1816.                 op_add16();

  1817.                 cf = oldcf;

  1818.                 regs.wordregs[regbx] = res16;

  1819.                 break;

  1820. 

  1821.             case 0x44:	/* 44 INC eSP */

  1822.                 oldcf = cf;

  1823.                 oper1 = regs.wordregs[regsp];

  1824.                 oper2 = 1;

  1825.                 op_add16();

  1826.                 cf = oldcf;

  1827.                 regs.wordregs[regsp] = res16;

  1828.                 break;

  1829. 

  1830.             case 0x45:	/* 45 INC eBP */

  1831.                 oldcf = cf;

  1832.                 oper1 = regs.wordregs[regbp];

  1833.                 oper2 = 1;

  1834.                 op_add16();

  1835.                 cf = oldcf;

  1836.                 regs.wordregs[regbp] = res16;

  1837.                 break;

  1838. 

  1839.             case 0x46:	/* 46 INC eSI */

  1840.                 oldcf = cf;

  1841.                 oper1 = regs.wordregs[regsi];

  1842.                 oper2 = 1;

  1843.                 op_add16();

  1844.                 cf = oldcf;

  1845.                 regs.wordregs[regsi] = res16;

  1846.                 break;

  1847. 

  1848.             case 0x47:	/* 47 INC eDI */

  1849.                 oldcf = cf;

  1850.                 oper1 = regs.wordregs[regdi];

  1851.                 oper2 = 1;

  1852.                 op_add16();

  1853.                 cf = oldcf;

  1854.                 regs.wordregs[regdi] = res16;

  1855.                 break;

  1856. 

  1857.             case 0x48:	/* 48 DEC eAX */

  1858.                 oldcf = cf;

  1859.                 oper1 = regs.wordregs[regax];

  1860.                 oper2 = 1;

  1861.                 op_sub16();

  1862.                 cf = oldcf;

  1863.                 regs.wordregs[regax] = res16;

  1864.                 break;

  1865. 

  1866.             case 0x49:	/* 49 DEC eCX */

  1867.                 oldcf = cf;

  1868.                 oper1 = regs.wordregs[regcx];

  1869.                 oper2 = 1;

  1870.                 op_sub16();

  1871.                 cf = oldcf;

  1872.                 regs.wordregs[regcx] = res16;

  1873.                 break;

  1874. 

  1875.             case 0x4A:	/* 4A DEC eDX */

  1876.                 oldcf = cf;

  1877.                 oper1 = regs.wordregs[regdx];

  1878.                 oper2 = 1;

  1879.                 op_sub16();

  1880.                 cf = oldcf;

  1881.                 regs.wordregs[regdx] = res16;

  1882.                 break;

  1883. 

  1884.             case 0x4B:	/* 4B DEC eBX */

  1885.                 oldcf = cf;

  1886.                 oper1 = regs.wordregs[regbx];

  1887.                 oper2 = 1;

  1888.                 op_sub16();

  1889.                 cf = oldcf;

  1890.                 regs.wordregs[regbx] = res16;

  1891.                 break;

  1892. 

  1893.             case 0x4C:	/* 4C DEC eSP */

  1894.                 oldcf = cf;

  1895.                 oper1 = regs.wordregs[regsp];

  1896.                 oper2 = 1;

  1897.                 op_sub16();

  1898.                 cf = oldcf;

  1899.                 regs.wordregs[regsp] = res16;

  1900.                 break;

  1901. 

  1902.             case 0x4D:	/* 4D DEC eBP */

  1903.                 oldcf = cf;

  1904.                 oper1 = regs.wordregs[regbp];

  1905.                 oper2 = 1;

  1906.                 op_sub16();

  1907.                 cf = oldcf;

  1908.                 regs.wordregs[regbp] = res16;

  1909.                 break;

  1910. 

  1911.             case 0x4E:	/* 4E DEC eSI */

  1912.                 oldcf = cf;

  1913.                 oper1 = regs.wordregs[regsi];

  1914.                 oper2 = 1;

  1915.                 op_sub16();

  1916.                 cf = oldcf;

  1917.                 regs.wordregs[regsi] = res16;

  1918.                 break;

  1919. 

  1920.             case 0x4F:	/* 4F DEC eDI */

  1921.                 oldcf = cf;

  1922.                 oper1 = regs.wordregs[regdi];

  1923.                 oper2 = 1;

  1924.                 op_sub16();

  1925.                 cf = oldcf;

  1926.                 regs.wordregs[regdi] = res16;

  1927.                 break;

  1928. 

  1929.             case 0x50:	/* 50 PUSH eAX */

  1930.                 push (regs.wordregs[regax]);

  1931.                 break;

  1932. 

  1933.             case 0x51:	/* 51 PUSH eCX */

  1934.                 push (regs.wordregs[regcx]);

  1935.                 break;

  1936. 

  1937.             case 0x52:	/* 52 PUSH eDX */

  1938.                 push (regs.wordregs[regdx]);

  1939.                 break;

  1940. 

  1941.             case 0x53:	/* 53 PUSH eBX */

  1942.                 push (regs.wordregs[regbx]);

  1943.                 break;

  1944. 

  1945.             case 0x54:	/* 54 PUSH eSP */

  1946. #ifdef USE_286_STYLE_PUSH_SP

  1947.                 push (regs.wordregs[regsp]);

  1948. #else

  1949.                 push (regs.wordregs[regsp] - 2);

  1950. #endif

  1951.                 break;

  1952. 

  1953.             case 0x55:	/* 55 PUSH eBP */

  1954.                 push (regs.wordregs[regbp]);

  1955.                 break;

  1956. 

  1957.             case 0x56:	/* 56 PUSH eSI */

  1958.                 push (regs.wordregs[regsi]);

  1959.                 break;

  1960. 

  1961.             case 0x57:	/* 57 PUSH eDI */

  1962.                 push (regs.wordregs[regdi]);

  1963.                 break;

  1964. 

  1965.             case 0x58:	/* 58 POP eAX */

  1966.                 regs.wordregs[regax] = pop();

  1967.                 break;

  1968. 

  1969.             case 0x59:	/* 59 POP eCX */

  1970.                 regs.wordregs[regcx] = pop();

  1971.                 break;

  1972. 

  1973.             case 0x5A:	/* 5A POP eDX */

  1974.                 regs.wordregs[regdx] = pop();

  1975.                 break;

  1976. 

  1977.             case 0x5B:	/* 5B POP eBX */

  1978.                 regs.wordregs[regbx] = pop();

  1979.                 break;

  1980. 

  1981.             case 0x5C:	/* 5C POP eSP */

  1982.                 regs.wordregs[regsp] = pop();

  1983.                 break;

  1984. 

  1985.             case 0x5D:	/* 5D POP eBP */

  1986.                 regs.wordregs[regbp] = pop();

  1987.                 break;

  1988. 

  1989.             case 0x5E:	/* 5E POP eSI */

  1990.                 regs.wordregs[regsi] = pop();

  1991.                 break;

  1992. 

  1993.             case 0x5F:	/* 5F POP eDI */

  1994.                 regs.wordregs[regdi] = pop();

  1995.                 break;

  1996. 

  1997. #ifndef CPU_8086

  1998.             case 0x60:	/* 60 PUSHA (80186+) */

  1999.                 oldsp = regs.wordregs[regsp];

  2000.                 push (regs.wordregs[regax]);

  2001.                 push (regs.wordregs[regcx]);

  2002.                 push (regs.wordregs[regdx]);

  2003.                 push (regs.wordregs[regbx]);

  2004.                 push (oldsp);

  2005.                 push (regs.wordregs[regbp]);

  2006.                 push (regs.wordregs[regsi]);

  2007.                 push (regs.wordregs[regdi]);

  2008.                 break;

  2009. 

  2010.             case 0x61:	/* 61 POPA (80186+) */

  2011.                 regs.wordregs[regdi] = pop();

  2012.                 regs.wordregs[regsi] = pop();

  2013.                 regs.wordregs[regbp] = pop();

  2014.                 dummy = pop();

  2015.                 regs.wordregs[regbx] = pop();

  2016.                 regs.wordregs[regdx] = pop();

  2017.                 regs.wordregs[regcx] = pop();

  2018.                 regs.wordregs[regax] = pop();

  2019.                 break;

  2020. 

  2021.             case 0x62: /* 62 BOUND Gv, Ev (80186+) */

  2022.                 modregrm();

  2023.                 getea (rm);

  2024.                 if (signext32 (getreg16 (reg) ) < signext32 ( getmem16 (ea >> 4, ea & 15) ) ) {

  2025.                         intcall86 (5); //bounds check exception

  2026.                     }

  2027.                 else {

  2028.                         ea += 2;

  2029.                         if (signext32 (getreg16 (reg) ) > signext32 ( getmem16 (ea >> 4, ea & 15) ) ) {

  2030.                                 intcall86(5); //bounds check exception

  2031.                             }

  2032.                     }

  2033.                 break;

  2034. 

  2035.             case 0x68:	/* 68 PUSH Iv (80186+) */

  2036.                 push (getmem16 (segregs[regcs], ip) );

  2037.                 StepIP (2);

  2038.                 break;

  2039. 

  2040.             case 0x69:	/* 69 IMUL Gv Ev Iv (80186+) */

  2041.                 modregrm();

  2042.                 temp1 = readrm16 (rm);

  2043.                 temp2 = getmem16 (segregs[regcs], ip);

  2044.                 StepIP (2);

  2045.                 if ( (temp1 & 0x8000L) == 0x8000L) {

  2046.                         temp1 = temp1 | 0xFFFF0000L;

  2047.                     }

  2048. 

  2049.                 if ( (temp2 & 0x8000L) == 0x8000L) {

  2050.                         temp2 = temp2 | 0xFFFF0000L;

  2051.                     }

  2052. 

  2053.                 temp3 = temp1 * temp2;

  2054.                 putreg16 (reg, temp3 & 0xFFFFL);

  2055.                 if (temp3 & 0xFFFF0000L) {

  2056.                         cf = 1;

  2057.                         of = 1;

  2058.                     }

  2059.                 else {

  2060.                         cf = 0;

  2061.                         of = 0;

  2062.                     }

  2063.                 break;

  2064. 

  2065.             case 0x6A:	/* 6A PUSH Ib (80186+) */

  2066.                 push (getmem8 (segregs[regcs], ip) );

  2067.                 StepIP (1);

  2068.                 break;

  2069. 

  2070.             case 0x6B:	/* 6B IMUL Gv Eb Ib (80186+) */

  2071.                 modregrm();

  2072.                 temp1 = readrm16 (rm);

  2073.                 temp2 = signext (getmem8 (segregs[regcs], ip) );

  2074.                 StepIP (1);

  2075.                 if ( (temp1 & 0x8000L) == 0x8000L) {

  2076.                         temp1 = temp1 | 0xFFFF0000L;

  2077.                     }

  2078. 

  2079.                 if ( (temp2 & 0x8000L) == 0x8000L) {

  2080.                         temp2 = temp2 | 0xFFFF0000L;

  2081.                     }

  2082. 

  2083.                 temp3 = temp1 * temp2;

  2084.                 putreg16 (reg, temp3 & 0xFFFFL);

  2085.                 if (temp3 & 0xFFFF0000L) {

  2086.                         cf = 1;

  2087.                         of = 1;

  2088.                     }

  2089.                 else {

  2090.                         cf = 0;

  2091.                         of = 0;

  2092.                     }

  2093.                 break;

  2094. 

  2095.             case 0x6C:	/* 6E INSB */

  2096.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2097.                         break;

  2098.                     }

  2099. 

  2100.                 putmem8 (useseg, regs.wordregs[regsi], portin (regs.wordregs[regdx]) );

  2101.                 if (df) {

  2102.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2103.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2104.                     }

  2105.                 else {

  2106.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2107.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2108.                     }

  2109. 

  2110.                 if (reptype) {

  2111.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2112.                     }

  2113. 

  2114.                 totalexec++;

  2115.                 loopcount++;

  2116.                 if (!reptype) {

  2117.                         break;

  2118.                     }

  2119. 

  2120.                 ip = firstip;

  2121.                 break;

  2122. 

  2123.             case 0x6D:	/* 6F INSW */

  2124.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2125.                         break;

  2126.                     }

  2127. 

  2128.                 putmem16 (useseg, regs.wordregs[regsi], portin16 (regs.wordregs[regdx]) );

  2129.                 if (df) {

  2130.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2131.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2132.                     }

  2133.                 else {

  2134.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2135.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2136.                     }

  2137. 

  2138.                 if (reptype) {

  2139.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2140.                     }

  2141. 

  2142.                 totalexec++;

  2143.                 loopcount++;

  2144.                 if (!reptype) {

  2145.                         break;

  2146.                     }

  2147. 

  2148.                 ip = firstip;

  2149.                 break;

  2150. 

  2151.             case 0x6E:	/* 6E OUTSB */

  2152.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2153.                         break;

  2154.                     }

  2155. 

  2156.                 portout (regs.wordregs[regdx], getmem8 (useseg, regs.wordregs[regsi]) );

  2157.                 if (df) {

  2158.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2159.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2160.                     }

  2161.                 else {

  2162.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2163.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2164.                     }

  2165. 

  2166.                 if (reptype) {

  2167.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2168.                     }

  2169. 

  2170.                 totalexec++;

  2171.                 loopcount++;

  2172.                 if (!reptype) {

  2173.                         break;

  2174.                     }

  2175. 

  2176.                 ip = firstip;

  2177.                 break;

  2178. 

  2179.             case 0x6F:	/* 6F OUTSW */

  2180.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2181.                         break;

  2182.                     }

  2183. 

  2184.                 portout16 (regs.wordregs[regdx], getmem16 (useseg, regs.wordregs[regsi]) );

  2185.                 if (df) {

  2186.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2187.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2188.                     }

  2189.                 else {

  2190.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2191.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2192.                     }

  2193. 

  2194.                 if (reptype) {

  2195.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2196.                     }

  2197. 

  2198.                 totalexec++;

  2199.                 loopcount++;

  2200.                 if (!reptype) {

  2201.                         break;

  2202.                     }

  2203. 

  2204.                 ip = firstip;

  2205.                 break;

  2206. #endif

  2207. 

  2208.             case 0x70:	/* 70 JO Jb */

  2209.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2210.                 StepIP (1);

  2211.                 if (of) {

  2212.                         ip = ip + temp16;

  2213.                     }

  2214.                 break;

  2215. 

  2216.             case 0x71:	/* 71 JNO Jb */

  2217.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2218.                 StepIP (1);

  2219.                 if (!of) {

  2220.                         ip = ip + temp16;

  2221.                     }

  2222.                 break;

  2223. 

  2224.             case 0x72:	/* 72 JB Jb */

  2225.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2226.                 StepIP (1);

  2227.                 if (cf) {

  2228.                         ip = ip + temp16;

  2229.                     }

  2230.                 break;

  2231. 

  2232.             case 0x73:	/* 73 JNB Jb */

  2233.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2234.                 StepIP (1);

  2235.                 if (!cf) {

  2236.                         ip = ip + temp16;

  2237.                     }

  2238.                 break;

  2239. 

  2240.             case 0x74:	/* 74 JZ Jb */

  2241.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2242.                 StepIP (1);

  2243.                 if (zf) {

  2244.                         ip = ip + temp16;

  2245.                     }

  2246.                 break;

  2247. 

  2248.             case 0x75:	/* 75 JNZ Jb */

  2249.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2250.                 StepIP (1);

  2251.                 if (!zf) {

  2252.                         ip = ip + temp16;

  2253.                     }

  2254.                 break;

  2255. 

  2256.             case 0x76:	/* 76 JBE Jb */

  2257.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2258.                 StepIP (1);

  2259.                 if (cf || zf) {

  2260.                         ip = ip + temp16;

  2261.                     }

  2262.                 break;

  2263. 

  2264.             case 0x77:	/* 77 JA Jb */

  2265.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2266.                 StepIP (1);

  2267.                 if (!cf && !zf) {

  2268.                         ip = ip + temp16;

  2269.                     }

  2270.                 break;

  2271. 

  2272.             case 0x78:	/* 78 JS Jb */

  2273.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2274.                 StepIP (1);

  2275.                 if (sf) {

  2276.                         ip = ip + temp16;

  2277.                     }

  2278.                 break;

  2279. 

  2280.             case 0x79:	/* 79 JNS Jb */

  2281.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2282.                 StepIP (1);

  2283.                 if (!sf) {

  2284.                         ip = ip + temp16;

  2285.                     }

  2286.                 break;

  2287. 

  2288.             case 0x7A:	/* 7A JPE Jb */

  2289.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2290.                 StepIP (1);

  2291.                 if (pf) {

  2292.                         ip = ip + temp16;

  2293.                     }

  2294.                 break;

  2295. 

  2296.             case 0x7B:	/* 7B JPO Jb */

  2297.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2298.                 StepIP (1);

  2299.                 if (!pf) {

  2300.                         ip = ip + temp16;

  2301.                     }

  2302.                 break;

  2303. 

  2304.             case 0x7C:	/* 7C JL Jb */

  2305.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2306.                 StepIP (1);

  2307.                 if (sf != of) {

  2308.                         ip = ip + temp16;

  2309.                     }

  2310.                 break;

  2311. 

  2312.             case 0x7D:	/* 7D JGE Jb */

  2313.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2314.                 StepIP (1);

  2315.                 if (sf == of) {

  2316.                         ip = ip + temp16;

  2317.                     }

  2318.                 break;

  2319. 

  2320.             case 0x7E:	/* 7E JLE Jb */

  2321.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2322.                 StepIP (1);

  2323.                 if ( (sf != of) || zf) {

  2324.                         ip = ip + temp16;

  2325.                     }

  2326.                 break;

  2327. 

  2328.             case 0x7F:	/* 7F JG Jb */

  2329.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  2330.                 StepIP (1);

  2331.                 if (!zf && (sf == of) ) {

  2332.                         ip = ip + temp16;

  2333.                     }

  2334.                 break;

  2335. 

  2336.             case 0x80:

  2337.             case 0x82:	/* 80/82 GRP1 Eb Ib */

  2338.                 modregrm();

  2339.                 oper1b = readrm8 (rm);

  2340.                 oper2b = getmem8 (segregs[regcs], ip);

  2341.                 StepIP (1);

  2342.                 switch (reg) {

  2343.                         case 0:

  2344.                             op_add8();

  2345.                             break;

  2346.                         case 1:

  2347.                             op_or8();

  2348.                             break;

  2349.                         case 2:

  2350.                             op_adc8();

  2351.                             break;

  2352.                         case 3:

  2353.                             op_sbb8();

  2354.                             break;

  2355.                         case 4:

  2356.                             op_and8();

  2357.                             break;

  2358.                         case 5:

  2359.                             op_sub8();

  2360.                             break;

  2361.                         case 6:

  2362.                             op_xor8();

  2363.                             break;

  2364.                         case 7:

  2365.                             flag_sub8 (oper1b, oper2b);

  2366.                             break;

  2367.                         default:

  2368.                             break;	/* to avoid compiler warnings */

  2369.                     }

  2370. 

  2371.                 if (reg < 7) {

  2372.                         writerm8 (rm, res8);

  2373.                     }

  2374.                 break;

  2375. 

  2376.             case 0x81:	/* 81 GRP1 Ev Iv */

  2377.             case 0x83:	/* 83 GRP1 Ev Ib */

  2378.                 modregrm();

  2379.                 oper1 = readrm16 (rm);

  2380.                 if (opcode == 0x81) {

  2381.                         oper2 = getmem16 (segregs[regcs], ip);

  2382.                         StepIP (2);

  2383.                     }

  2384.                 else {

  2385.                         oper2 = signext (getmem8 (segregs[regcs], ip) );

  2386.                         StepIP (1);

  2387.                     }

  2388. 

  2389.                 switch (reg) {

  2390.                         case 0:

  2391.                             op_add16();

  2392.                             break;

  2393.                         case 1:

  2394.                             op_or16();

  2395.                             break;

  2396.                         case 2:

  2397.                             op_adc16();

  2398.                             break;

  2399.                         case 3:

  2400.                             op_sbb16();

  2401.                             break;

  2402.                         case 4:

  2403.                             op_and16();

  2404.                             break;

  2405.                         case 5:

  2406.                             op_sub16();

  2407.                             break;

  2408.                         case 6:

  2409.                             op_xor16();

  2410.                             break;

  2411.                         case 7:

  2412.                             flag_sub16 (oper1, oper2);

  2413.                             break;

  2414.                         default:

  2415.                             break;	/* to avoid compiler warnings */

  2416.                     }

  2417. 

  2418.                 if (reg < 7) {

  2419.                         writerm16 (rm, res16);

  2420.                     }

  2421.                 break;

  2422. 

  2423.             case 0x84:	/* 84 TEST Gb Eb */

  2424.                 modregrm();

  2425.                 oper1b = getreg8 (reg);

  2426.                 oper2b = readrm8 (rm);

  2427.                 flag_log8 (oper1b & oper2b);

  2428.                 break;

  2429. 

  2430.             case 0x85:	/* 85 TEST Gv Ev */

  2431.                 modregrm();

  2432.                 oper1 = getreg16 (reg);

  2433.                 oper2 = readrm16 (rm);

  2434.                 flag_log16 (oper1 & oper2);

  2435.                 break;

  2436. 

  2437.             case 0x86:	/* 86 XCHG Gb Eb */

  2438.                 modregrm();

  2439.                 oper1b = getreg8 (reg);

  2440.                 putreg8 (reg, readrm8 (rm) );

  2441.                 writerm8 (rm, oper1b);

  2442.                 break;

  2443. 

  2444.             case 0x87:	/* 87 XCHG Gv Ev */

  2445.                 modregrm();

  2446.                 oper1 = getreg16 (reg);

  2447.                 putreg16 (reg, readrm16 (rm) );

  2448.                 writerm16 (rm, oper1);

  2449.                 break;

  2450. 

  2451.             case 0x88:	/* 88 MOV Eb Gb */

  2452.                 modregrm();

  2453.                 writerm8 (rm, getreg8 (reg) );

  2454.                 break;

  2455. 

  2456.             case 0x89:	/* 89 MOV Ev Gv */

  2457.                 modregrm();

  2458.                 writerm16 (rm, getreg16 (reg) );

  2459.                 break;

  2460. 

  2461.             case 0x8A:	/* 8A MOV Gb Eb */

  2462.                 modregrm();

  2463.                 putreg8 (reg, readrm8 (rm) );

  2464.                 break;

  2465. 

  2466.             case 0x8B:	/* 8B MOV Gv Ev */

  2467.                 modregrm();

  2468.                 putreg16 (reg, readrm16 (rm) );

  2469.                 break;

  2470. 

  2471.             case 0x8C:	/* 8C MOV Ew Sw */

  2472.                 modregrm();

  2473.                 writerm16 (rm, getsegreg (reg) );

  2474.                 break;

  2475. 

  2476.             case 0x8D:	/* 8D LEA Gv M */

  2477.                 modregrm();

  2478.                 getea (rm);

  2479.                 putreg16 (reg, ea - segbase (useseg) );

  2480.                 break;

  2481. 

  2482.             case 0x8E:	/* 8E MOV Sw Ew */

  2483.                 modregrm();

  2484.                 putsegreg (reg, readrm16 (rm) );

  2485.                 break;

  2486. 

  2487.             case 0x8F:	/* 8F POP Ev */

  2488.                 modregrm();

  2489.                 writerm16 (rm, pop() );

  2490.                 break;

  2491. 

  2492.             case 0x90:	/* 90 NOP */

  2493.                 break;

  2494. 

  2495.             case 0x91:	/* 91 XCHG eCX eAX */

  2496.                 oper1 = regs.wordregs[regcx];

  2497.                 regs.wordregs[regcx] = regs.wordregs[regax];

  2498.                 regs.wordregs[regax] = oper1;

  2499.                 break;

  2500. 

  2501.             case 0x92:	/* 92 XCHG eDX eAX */

  2502.                 oper1 = regs.wordregs[regdx];

  2503.                 regs.wordregs[regdx] = regs.wordregs[regax];

  2504.                 regs.wordregs[regax] = oper1;

  2505.                 break;

  2506. 

  2507.             case 0x93:	/* 93 XCHG eBX eAX */

  2508.                 oper1 = regs.wordregs[regbx];

  2509.                 regs.wordregs[regbx] = regs.wordregs[regax];

  2510.                 regs.wordregs[regax] = oper1;

  2511.                 break;

  2512. 

  2513.             case 0x94:	/* 94 XCHG eSP eAX */

  2514.                 oper1 = regs.wordregs[regsp];

  2515.                 regs.wordregs[regsp] = regs.wordregs[regax];

  2516.                 regs.wordregs[regax] = oper1;

  2517.                 break;

  2518. 

  2519.             case 0x95:	/* 95 XCHG eBP eAX */

  2520.                 oper1 = regs.wordregs[regbp];

  2521.                 regs.wordregs[regbp] = regs.wordregs[regax];

  2522.                 regs.wordregs[regax] = oper1;

  2523.                 break;

  2524. 

  2525.             case 0x96:	/* 96 XCHG eSI eAX */

  2526.                 oper1 = regs.wordregs[regsi];

  2527.                 regs.wordregs[regsi] = regs.wordregs[regax];

  2528.                 regs.wordregs[regax] = oper1;

  2529.                 break;

  2530. 

  2531.             case 0x97:	/* 97 XCHG eDI eAX */

  2532.                 oper1 = regs.wordregs[regdi];

  2533.                 regs.wordregs[regdi] = regs.wordregs[regax];

  2534.                 regs.wordregs[regax] = oper1;

  2535.                 break;

  2536. 

  2537.             case 0x98:	/* 98 CBW */

  2538.                 if ( (regs.byteregs[regal] & 0x80) == 0x80) {

  2539.                         regs.byteregs[regah] = 0xFF;

  2540.                     }

  2541.                 else {

  2542.                         regs.byteregs[regah] = 0;

  2543.                     }

  2544.                 break;

  2545. 

  2546.             case 0x99:	/* 99 CWD */

  2547.                 if ( (regs.byteregs[regah] & 0x80) == 0x80) {

  2548.                         regs.wordregs[regdx] = 0xFFFF;

  2549.                     }

  2550.                 else {

  2551.                         regs.wordregs[regdx] = 0;

  2552.                     }

  2553.                 break;

  2554. 

  2555.             case 0x9A:	/* 9A CALL Ap */

  2556.                 oper1 = getmem16 (segregs[regcs], ip);

  2557.                 StepIP (2);

  2558.                 oper2 = getmem16 (segregs[regcs], ip);

  2559.                 StepIP (2);

  2560.                 push (segregs[regcs]);

  2561.                 push (ip);

  2562.                 ip = oper1;

  2563.                 segregs[regcs] = oper2;

  2564.                 break;

  2565. 

  2566.             case 0x9B:	/* 9B WAIT */

  2567.                 break;

  2568. 

  2569.             case 0x9C:	/* 9C PUSHF */

  2570. #ifdef CPU_SET_HIGH_FLAGS

  2571.                 push (makeflagsword() | 0xF800);

  2572. #else

  2573.                 push (makeflagsword() | 0x0800);

  2574. #endif

  2575.                 break;

  2576. 

  2577.             case 0x9D:	/* 9D POPF */

  2578.                 temp16 = pop();

  2579.                 decodeflagsword (temp16);

  2580.                 break;

  2581. 

  2582.             case 0x9E:	/* 9E SAHF */

  2583.                 decodeflagsword ( (makeflagsword() & 0xFF00) | regs.byteregs[regah]);

  2584.                 break;

  2585. 

  2586.             case 0x9F:	/* 9F LAHF */

  2587.                 regs.byteregs[regah] = makeflagsword() & 0xFF;

  2588.                 break;

  2589. 

  2590.             case 0xA0:	/* A0 MOV regs.byteregs[regal] Ob */

  2591.                 regs.byteregs[regal] = getmem8 (useseg, getmem16 (segregs[regcs], ip) );

  2592.                 StepIP (2);

  2593.                 break;

  2594. 

  2595.             case 0xA1:	/* A1 MOV eAX Ov */

  2596.                 oper1 = getmem16 (useseg, getmem16 (segregs[regcs], ip) );

  2597.                 StepIP (2);

  2598.                 regs.wordregs[regax] = oper1;

  2599.                 break;

  2600. 

  2601.             case 0xA2:	/* A2 MOV Ob regs.byteregs[regal] */

  2602.                 putmem8 (useseg, getmem16 (segregs[regcs], ip), regs.byteregs[regal]);

  2603.                 StepIP (2);

  2604.                 break;

  2605. 

  2606.             case 0xA3:	/* A3 MOV Ov eAX */

  2607.                 putmem16 (useseg, getmem16 (segregs[regcs], ip), regs.wordregs[regax]);

  2608.                 StepIP (2);

  2609.                 break;

  2610. 

  2611.             case 0xA4:	/* A4 MOVSB */

  2612.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2613.                         break;

  2614.                     }

  2615. 

  2616.                 putmem8 (segregs[reges], regs.wordregs[regdi], getmem8 (useseg, regs.wordregs[regsi]) );

  2617.                 if (df) {

  2618.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2619.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2620.                     }

  2621.                 else {

  2622.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2623.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2624.                     }

  2625. 

  2626.                 if (reptype) {

  2627.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2628.                     }

  2629. 

  2630.                 totalexec++;

  2631.                 loopcount++;

  2632.                 if (!reptype) {

  2633.                         break;

  2634.                     }

  2635. 

  2636.                 ip = firstip;

  2637.                 break;

  2638. 

  2639.             case 0xA5:	/* A5 MOVSW */

  2640.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2641.                         break;

  2642.                     }

  2643. 

  2644.                 putmem16 (segregs[reges], regs.wordregs[regdi], getmem16 (useseg, regs.wordregs[regsi]) );

  2645.                 if (df) {

  2646.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2647.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2648.                     }

  2649.                 else {

  2650.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2651.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2652.                     }

  2653. 

  2654.                 if (reptype) {

  2655.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2656.                     }

  2657. 

  2658.                 totalexec++;

  2659.                 loopcount++;

  2660.                 if (!reptype) {

  2661.                         break;

  2662.                     }

  2663. 

  2664.                 ip = firstip;

  2665.                 break;

  2666. 

  2667.             case 0xA6:	/* A6 CMPSB */

  2668.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2669.                         break;

  2670.                     }

  2671. 

  2672.                 oper1b = getmem8 (useseg, regs.wordregs[regsi]);

  2673.                 oper2b = getmem8 (segregs[reges], regs.wordregs[regdi]);

  2674.                 if (df) {

  2675.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2676.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2677.                     }

  2678.                 else {

  2679.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2680.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2681.                     }

  2682. 

  2683.                 flag_sub8 (oper1b, oper2b);

  2684.                 if (reptype) {

  2685.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2686.                     }

  2687. 

  2688.                 if ( (reptype == 1) && !zf) {

  2689.                         break;

  2690.                     }

  2691.                 else if ( (reptype == 2) && (zf == 1) ) {

  2692.                         break;

  2693.                     }

  2694. 

  2695.                 totalexec++;

  2696.                 loopcount++;

  2697.                 if (!reptype) {

  2698.                         break;

  2699.                     }

  2700. 

  2701.                 ip = firstip;

  2702.                 break;

  2703. 

  2704.             case 0xA7:	/* A7 CMPSW */

  2705.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2706.                         break;

  2707.                     }

  2708. 

  2709.                 oper1 = getmem16 (useseg,regs.wordregs[regsi]);

  2710.                 oper2 = getmem16 (segregs[reges], regs.wordregs[regdi]);

  2711.                 if (df) {

  2712.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2713.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2714.                     }

  2715.                 else {

  2716.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2717.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2718.                     }

  2719. 

  2720.                 flag_sub16 (oper1, oper2);

  2721.                 if (reptype) {

  2722.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2723.                     }

  2724. 

  2725.                 if ( (reptype == 1) && !zf) {

  2726.                         break;

  2727.                     }

  2728. 

  2729.                 if ( (reptype == 2) && (zf == 1) ) {

  2730.                         break;

  2731.                     }

  2732. 

  2733.                 totalexec++;

  2734.                 loopcount++;

  2735.                 if (!reptype) {

  2736.                         break;

  2737.                     }

  2738. 

  2739.                 ip = firstip;

  2740.                 break;

  2741. 

  2742.             case 0xA8:	/* A8 TEST regs.byteregs[regal] Ib */

  2743.                 oper1b = regs.byteregs[regal];

  2744.                 oper2b = getmem8 (segregs[regcs], ip);

  2745.                 StepIP (1);

  2746.                 flag_log8 (oper1b & oper2b);

  2747.                 break;

  2748. 

  2749.             case 0xA9:	/* A9 TEST eAX Iv */

  2750.                 oper1 = regs.wordregs[regax];

  2751.                 oper2 = getmem16 (segregs[regcs], ip);

  2752.                 StepIP (2);

  2753.                 flag_log16 (oper1 & oper2);

  2754.                 break;

  2755. 

  2756.             case 0xAA:	/* AA STOSB */

  2757.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2758.                         break;

  2759.                     }

  2760. 

  2761.                 putmem8 (segregs[reges], regs.wordregs[regdi], regs.byteregs[regal]);

  2762.                 if (df) {

  2763.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2764.                     }

  2765.                 else {

  2766.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2767.                     }

  2768. 

  2769.                 if (reptype) {

  2770.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2771.                     }

  2772. 

  2773.                 totalexec++;

  2774.                 loopcount++;

  2775.                 if (!reptype) {

  2776.                         break;

  2777.                     }

  2778. 

  2779.                 ip = firstip;

  2780.                 break;

  2781. 

  2782.             case 0xAB:	/* AB STOSW */

  2783.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2784.                         break;

  2785.                     }

  2786. 

  2787.                 putmem16 (segregs[reges], regs.wordregs[regdi], regs.wordregs[regax]);

  2788.                 if (df) {

  2789.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2790.                     }

  2791.                 else {

  2792.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2793.                     }

  2794. 

  2795.                 if (reptype) {

  2796.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2797.                     }

  2798. 

  2799.                 totalexec++;

  2800.                 loopcount++;

  2801.                 if (!reptype) {

  2802.                         break;

  2803.                     }

  2804. 

  2805.                 ip = firstip;

  2806.                 break;

  2807. 

  2808.             case 0xAC:	/* AC LODSB */

  2809.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2810.                         break;

  2811.                     }

  2812. 

  2813.                 regs.byteregs[regal] = getmem8 (useseg, regs.wordregs[regsi]);

  2814.                 if (df) {

  2815.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 1;

  2816.                     }

  2817.                 else {

  2818.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 1;

  2819.                     }

  2820. 

  2821.                 if (reptype) {

  2822.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2823.                     }

  2824. 

  2825.                 totalexec++;

  2826.                 loopcount++;

  2827.                 if (!reptype) {

  2828.                         break;

  2829.                     }

  2830. 

  2831.                 ip = firstip;

  2832.                 break;

  2833. 

  2834.             case 0xAD:	/* AD LODSW */

  2835.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2836.                         break;

  2837.                     }

  2838. 

  2839.                 oper1 = getmem16 (useseg, regs.wordregs[regsi]);

  2840.                 regs.wordregs[regax] = oper1;

  2841.                 if (df) {

  2842.                         regs.wordregs[regsi] = regs.wordregs[regsi] - 2;

  2843.                     }

  2844.                 else {

  2845.                         regs.wordregs[regsi] = regs.wordregs[regsi] + 2;

  2846.                     }

  2847. 

  2848.                 if (reptype) {

  2849.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2850.                     }

  2851. 

  2852.                 totalexec++;

  2853.                 loopcount++;

  2854.                 if (!reptype) {

  2855.                         break;

  2856.                     }

  2857. 

  2858.                 ip = firstip;

  2859.                 break;

  2860. 

  2861.             case 0xAE:	/* AE SCASB */

  2862.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2863.                         break;

  2864.                     }

  2865. 

  2866.                 oper1b = regs.byteregs[regal];

  2867.                 oper2b = getmem8 (segregs[reges], regs.wordregs[regdi]);

  2868.                 flag_sub8 (oper1b, oper2b);

  2869.                 if (df) {

  2870.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 1;

  2871.                     }

  2872.                 else {

  2873.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 1;

  2874.                     }

  2875. 

  2876.                 if (reptype) {

  2877.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2878.                     }

  2879. 

  2880.                 if ( (reptype == 1) && !zf) {

  2881.                         break;

  2882.                     }

  2883.                 else if ( (reptype == 2) && (zf == 1) ) {

  2884.                         break;

  2885.                     }

  2886. 

  2887.                 totalexec++;

  2888.                 loopcount++;

  2889.                 if (!reptype) {

  2890.                         break;

  2891.                     }

  2892. 

  2893.                 ip = firstip;

  2894.                 break;

  2895. 

  2896.             case 0xAF:	/* AF SCASW */

  2897.                 if (reptype && (regs.wordregs[regcx] == 0) ) {

  2898.                         break;

  2899.                     }

  2900. 

  2901.                 oper1 = regs.wordregs[regax];

  2902.                 oper2 = getmem16 (segregs[reges], regs.wordregs[regdi]);

  2903.                 flag_sub16 (oper1, oper2);

  2904.                 if (df) {

  2905.                         regs.wordregs[regdi] = regs.wordregs[regdi] - 2;

  2906.                     }

  2907.                 else {

  2908.                         regs.wordregs[regdi] = regs.wordregs[regdi] + 2;

  2909.                     }

  2910. 

  2911.                 if (reptype) {

  2912.                         regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  2913.                     }

  2914. 

  2915.                 if ( (reptype == 1) && !zf) {

  2916.                         break;

  2917.                     }

  2918.                 else if ( (reptype == 2) & (zf == 1) ) {

  2919.                         break;

  2920.                     }

  2921. 

  2922.                 totalexec++;

  2923.                 loopcount++;

  2924.                 if (!reptype) {

  2925.                         break;

  2926.                     }

  2927. 

  2928.                 ip = firstip;

  2929.                 break;

  2930. 

  2931.             case 0xB0:	/* B0 MOV regs.byteregs[regal] Ib */

  2932.                 regs.byteregs[regal] = getmem8 (segregs[regcs], ip);

  2933.                 StepIP (1);

  2934.                 break;

  2935. 

  2936.             case 0xB1:	/* B1 MOV regs.byteregs[regcl] Ib */

  2937.                 regs.byteregs[regcl] = getmem8 (segregs[regcs], ip);

  2938.                 StepIP (1);

  2939.                 break;

  2940. 

  2941.             case 0xB2:	/* B2 MOV regs.byteregs[regdl] Ib */

  2942.                 regs.byteregs[regdl] = getmem8 (segregs[regcs], ip);

  2943.                 StepIP (1);

  2944.                 break;

  2945. 

  2946.             case 0xB3:	/* B3 MOV regs.byteregs[regbl] Ib */

  2947.                 regs.byteregs[regbl] = getmem8 (segregs[regcs], ip);

  2948.                 StepIP (1);

  2949.                 break;

  2950. 

  2951.             case 0xB4:	/* B4 MOV regs.byteregs[regah] Ib */

  2952.                 regs.byteregs[regah] = getmem8 (segregs[regcs], ip);

  2953.                 StepIP (1);

  2954.                 break;

  2955. 

  2956.             case 0xB5:	/* B5 MOV regs.byteregs[regch] Ib */

  2957.                 regs.byteregs[regch] = getmem8 (segregs[regcs], ip);

  2958.                 StepIP (1);

  2959.                 break;

  2960. 

  2961.             case 0xB6:	/* B6 MOV regs.byteregs[regdh] Ib */

  2962.                 regs.byteregs[regdh] = getmem8 (segregs[regcs], ip);

  2963.                 StepIP (1);

  2964.                 break;

  2965. 

  2966.             case 0xB7:	/* B7 MOV regs.byteregs[regbh] Ib */

  2967.                 regs.byteregs[regbh] = getmem8 (segregs[regcs], ip);

  2968.                 StepIP (1);

  2969.                 break;

  2970. 

  2971.             case 0xB8:	/* B8 MOV eAX Iv */

  2972.                 oper1 = getmem16 (segregs[regcs], ip);

  2973.                 StepIP (2);

  2974.                 regs.wordregs[regax] = oper1;

  2975.                 break;

  2976. 

  2977.             case 0xB9:	/* B9 MOV eCX Iv */

  2978.                 oper1 = getmem16 (segregs[regcs], ip);

  2979.                 StepIP (2);

  2980.                 regs.wordregs[regcx] = oper1;

  2981.                 break;

  2982. 

  2983.             case 0xBA:	/* BA MOV eDX Iv */

  2984.                 oper1 = getmem16 (segregs[regcs], ip);

  2985.                 StepIP (2);

  2986.                 regs.wordregs[regdx] = oper1;

  2987.                 break;

  2988. 

  2989.             case 0xBB:	/* BB MOV eBX Iv */

  2990.                 oper1 = getmem16 (segregs[regcs], ip);

  2991.                 StepIP (2);

  2992.                 regs.wordregs[regbx] = oper1;

  2993.                 break;

  2994. 

  2995.             case 0xBC:	/* BC MOV eSP Iv */

  2996.                 regs.wordregs[regsp] = getmem16 (segregs[regcs], ip);

  2997.                 StepIP (2);

  2998.                 break;

  2999. 

  3000.             case 0xBD:	/* BD MOV eBP Iv */

  3001.                 regs.wordregs[regbp] = getmem16 (segregs[regcs], ip);

  3002.                 StepIP (2);

  3003.                 break;

  3004. 

  3005.             case 0xBE:	/* BE MOV eSI Iv */

  3006.                 regs.wordregs[regsi] = getmem16 (segregs[regcs], ip);

  3007.                 StepIP (2);

  3008.                 break;

  3009. 

  3010.             case 0xBF:	/* BF MOV eDI Iv */

  3011.                 regs.wordregs[regdi] = getmem16 (segregs[regcs], ip);

  3012.                 StepIP (2);

  3013.                 break;

  3014. 

  3015.             case 0xC0:	/* C0 GRP2 byte imm8 (80186+) */

  3016.                 modregrm();

  3017.                 oper1b = readrm8 (rm);

  3018.                 oper2b = getmem8 (segregs[regcs], ip);

  3019.                 StepIP (1);

  3020.                 writerm8 (rm, op_grp2_8 (oper2b) );

  3021.                 break;

  3022. 

  3023.             case 0xC1:	/* C1 GRP2 word imm8 (80186+) */

  3024.                 modregrm();

  3025.                 oper1 = readrm16 (rm);

  3026.                 oper2 = getmem8 (segregs[regcs], ip);

  3027.                 StepIP (1);

  3028.                 writerm16 (rm, op_grp2_16 ( (uint8_t) oper2) );

  3029.                 break;

  3030. 

  3031.             case 0xC2:	/* C2 RET Iw */

  3032.                 oper1 = getmem16 (segregs[regcs], ip);

  3033.                 ip = pop();

  3034.                 regs.wordregs[regsp] = regs.wordregs[regsp] + oper1;

  3035.                 break;

  3036. 

  3037.             case 0xC3:	/* C3 RET */

  3038.                 ip = pop();

  3039.                 break;

  3040. 

  3041.             case 0xC4:	/* C4 LES Gv Mp */

  3042.                 modregrm();

  3043.                 getea (rm);

  3044.                 putreg16 (reg, read86 (ea) + read86 (ea + 1) * 256);

  3045.                 segregs[reges] = read86 (ea + 2) + read86 (ea + 3) * 256;

  3046.                 break;

  3047. 

  3048.             case 0xC5:	/* C5 LDS Gv Mp */

  3049.                 modregrm();

  3050.                 getea (rm);

  3051.                 putreg16 (reg, read86 (ea) + read86 (ea + 1) * 256);

  3052.                 segregs[regds] = read86 (ea + 2) + read86 (ea + 3) * 256;

  3053.                 break;

  3054. 

  3055.             case 0xC6:	/* C6 MOV Eb Ib */

  3056.                 modregrm();

  3057.                 writerm8 (rm, getmem8 (segregs[regcs], ip) );

  3058.                 StepIP (1);

  3059.                 break;

  3060. 

  3061.             case 0xC7:	/* C7 MOV Ev Iv */

  3062.                 modregrm();

  3063.                 writerm16 (rm, getmem16 (segregs[regcs], ip) );

  3064.                 StepIP (2);

  3065.                 break;

  3066. 

  3067.             case 0xC8:	/* C8 ENTER (80186+) */

  3068.                 stacksize = getmem16 (segregs[regcs], ip);

  3069.                 StepIP (2);

  3070.                 nestlev = getmem8 (segregs[regcs], ip);

  3071.                 StepIP (1);

  3072.                 push (regs.wordregs[regbp]);

  3073.                 frametemp = regs.wordregs[regsp];

  3074.                 if (nestlev) {

  3075.                         for (temp16 = 1; temp16 < nestlev; temp16++) {

  3076.                                 regs.wordregs[regbp] = regs.wordregs[regbp] - 2;

  3077.                                 push (regs.wordregs[regbp]);

  3078.                             }

  3079. 

  3080.                         push (regs.wordregs[regsp]);

  3081.                     }

  3082. 

  3083.                 regs.wordregs[regbp] = frametemp;

  3084.                 regs.wordregs[regsp] = regs.wordregs[regbp] - stacksize;

  3085. 

  3086.                 break;

  3087. 

  3088.             case 0xC9:	/* C9 LEAVE (80186+) */

  3089.                 regs.wordregs[regsp] = regs.wordregs[regbp];

  3090.                 regs.wordregs[regbp] = pop();

  3091.                 break;

  3092. 

  3093.             case 0xCA:	/* CA RETF Iw */

  3094.                 oper1 = getmem16 (segregs[regcs], ip);

  3095.                 ip = pop();

  3096.                 segregs[regcs] = pop();

  3097.                 regs.wordregs[regsp] = regs.wordregs[regsp] + oper1;

  3098.                 break;

  3099. 

  3100.             case 0xCB:	/* CB RETF */

  3101.                 ip = pop();;

  3102.                 segregs[regcs] = pop();

  3103.                 break;

  3104. 

  3105.             case 0xCC:	/* CC INT 3 */

  3106.                 intcall86 (3);

  3107.                 break;

  3108. 

  3109.             case 0xCD:	/* CD INT Ib */

  3110.                 oper1b = getmem8 (segregs[regcs], ip);

  3111.                 StepIP (1);

  3112.                 intcall86 (oper1b);

  3113.                 break;

  3114. 

  3115.             case 0xCE:	/* CE INTO */

  3116.                 if (of) {

  3117.                         intcall86 (4);

  3118.                     }

  3119.                 break;

  3120. 

  3121.             case 0xCF:	/* CF IRET */

  3122.                 ip = pop();

  3123.                 segregs[regcs] = pop();

  3124.                 decodeflagsword (pop() );

  3125. 

  3126.                 /*

  3127.                  * if (net.enabled) net.canrecv = 1;

  3128.                  */

  3129.                 break;

  3130. 

  3131.             case 0xD0:	/* D0 GRP2 Eb 1 */

  3132.                 modregrm();

  3133.                 oper1b = readrm8 (rm);

  3134.                 writerm8 (rm, op_grp2_8 (1) );

  3135.                 break;

  3136. 

  3137.             case 0xD1:	/* D1 GRP2 Ev 1 */

  3138.                 modregrm();

  3139.                 oper1 = readrm16 (rm);

  3140.                 writerm16 (rm, op_grp2_16 (1) );

  3141.                 break;

  3142. 

  3143.             case 0xD2:	/* D2 GRP2 Eb regs.byteregs[regcl] */

  3144.                 modregrm();

  3145.                 oper1b = readrm8 (rm);

  3146.                 writerm8 (rm, op_grp2_8 (regs.byteregs[regcl]) );

  3147.                 break;

  3148. 

  3149.             case 0xD3:	/* D3 GRP2 Ev regs.byteregs[regcl] */

  3150.                 modregrm();

  3151.                 oper1 = readrm16 (rm);

  3152.                 writerm16 (rm, op_grp2_16 (regs.byteregs[regcl]) );

  3153.                 break;

  3154. 

  3155.             case 0xD4:	/* D4 AAM I0 */

  3156.                 oper1 = getmem8 (segregs[regcs], ip);

  3157.                 StepIP (1);

  3158.                 if (!oper1) {

  3159.                         intcall86 (0);

  3160.                         break;

  3161.                     }	/* division by zero */

  3162. 

  3163.                 regs.byteregs[regah] = (regs.byteregs[regal] / oper1) & 255;

  3164.                 regs.byteregs[regal] = (regs.byteregs[regal] % oper1) & 255;

  3165.                 flag_szp16 (regs.wordregs[regax]);

  3166.                 break;

  3167. 

  3168.             case 0xD5:	/* D5 AAD I0 */

  3169.                 oper1 = getmem8 (segregs[regcs], ip);

  3170.                 StepIP (1);

  3171.                 regs.byteregs[regal] = (regs.byteregs[regah] * oper1 + regs.byteregs[regal]) & 255;

  3172.                 regs.byteregs[regah] = 0;

  3173.                 flag_szp16 (regs.byteregs[regah] * oper1 + regs.byteregs[regal]);

  3174.                 sf = 0;

  3175.                 break;

  3176. 

  3177.             case 0xD6:	/* D6 XLAT on V20/V30, SALC on 8086/8088 */

  3178. #ifndef CPU_NO_SALC

  3179.                 regs.byteregs[regal] = cf ? 0xFF : 0x00;

  3180.                 break;

  3181. #endif

  3182. 

  3183.             case 0xD7:	/* D7 XLAT */

  3184.                 regs.byteregs[regal] = read86(useseg * 16 + (regs.wordregs[regbx]) + regs.byteregs[regal]);

  3185.                 break;

  3186. 

  3187.             case 0xD8:

  3188.             case 0xD9:

  3189.             case 0xDA:

  3190.             case 0xDB:

  3191.             case 0xDC:

  3192.             case 0xDE:

  3193.             case 0xDD:

  3194.             case 0xDF:	/* escape to x87 FPU (unsupported) */

  3195.                 modregrm();

  3196.                 break;

  3197. 

  3198.             case 0xE0:	/* E0 LOOPNZ Jb */

  3199.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3200.                 StepIP (1);

  3201.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3202.                 if ( (regs.wordregs[regcx]) && !zf) {

  3203.                         ip = ip + temp16;

  3204.                     }

  3205.                 break;

  3206. 

  3207.             case 0xE1:	/* E1 LOOPZ Jb */

  3208.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3209.                 StepIP (1);

  3210.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3211.                 if (regs.wordregs[regcx] && (zf == 1) ) {

  3212.                         ip = ip + temp16;

  3213.                     }

  3214.                 break;

  3215. 

  3216.             case 0xE2:	/* E2 LOOP Jb */

  3217.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3218.                 StepIP (1);

  3219.                 regs.wordregs[regcx] = regs.wordregs[regcx] - 1;

  3220.                 if (regs.wordregs[regcx]) {

  3221.                         ip = ip + temp16;

  3222.                     }

  3223.                 break;

  3224. 

  3225.             case 0xE3:	/* E3 JCXZ Jb */

  3226.                 temp16 = signext (getmem8 (segregs[regcs], ip) );

  3227.                 StepIP (1);

  3228.                 if (!regs.wordregs[regcx]) {

  3229.                         ip = ip + temp16;

  3230.                     }

  3231.                 break;

  3232. 

  3233.             case 0xE4:	/* E4 IN regs.byteregs[regal] Ib */

  3234.                 oper1b = getmem8 (segregs[regcs], ip);

  3235.                 StepIP (1);

  3236.                 regs.byteregs[regal] = (uint8_t) portin (oper1b);

  3237.                 break;

  3238. 

  3239.             case 0xE5:	/* E5 IN eAX Ib */

  3240.                 oper1b = getmem8 (segregs[regcs], ip);

  3241.                 StepIP (1);

  3242.                 regs.wordregs[regax] = portin16 (oper1b);

  3243.                 break;

  3244. 

  3245.             case 0xE6:	/* E6 OUT Ib regs.byteregs[regal] */

  3246.                 oper1b = getmem8 (segregs[regcs], ip);

  3247.                 StepIP (1);

  3248.                 portout (oper1b, regs.byteregs[regal]);

  3249.                 break;

  3250. 

  3251.             case 0xE7:	/* E7 OUT Ib eAX */

  3252.                 oper1b = getmem8 (segregs[regcs], ip);

  3253.                 StepIP (1);

  3254.                 portout16 (oper1b, regs.wordregs[regax]);

  3255.                 break;

  3256. 

  3257.             case 0xE8:	/* E8 CALL Jv */

  3258.                 oper1 = getmem16 (segregs[regcs], ip);

  3259.                 StepIP (2);

  3260.                 push (ip);

  3261.                 ip = ip + oper1;

  3262.                 break;

  3263. 

  3264.             case 0xE9:	/* E9 JMP Jv */

  3265.                 oper1 = getmem16 (segregs[regcs], ip);

  3266.                 StepIP (2);

  3267.                 ip = ip + oper1;

  3268.                 break;

  3269. 

  3270.             case 0xEA:	/* EA JMP Ap */

  3271.                 oper1 = getmem16 (segregs[regcs], ip);

  3272.                 StepIP (2);

  3273.                 oper2 = getmem16 (segregs[regcs], ip);

  3274.                 ip = oper1;

  3275.                 segregs[regcs] = oper2;

  3276.                 break;

  3277. 

  3278.             case 0xEB:	/* EB JMP Jb */

  3279.                 oper1 = signext (getmem8 (segregs[regcs], ip) );

  3280.                 StepIP (1);

  3281.                 ip = ip + oper1;

  3282.                 break;

  3283. 

  3284.             case 0xEC:	/* EC IN regs.byteregs[regal] regdx */

  3285.                 oper1 = regs.wordregs[regdx];

  3286.                 regs.byteregs[regal] = (uint8_t) portin (oper1);

  3287.                 break;

  3288. 

  3289.             case 0xED:	/* ED IN eAX regdx */

  3290.                 oper1 = regs.wordregs[regdx];

  3291.                 regs.wordregs[regax] = portin16 (oper1);

  3292.                 break;

  3293. 

  3294.             case 0xEE:	/* EE OUT regdx regs.byteregs[regal] */

  3295.                 oper1 = regs.wordregs[regdx];

  3296.                 portout (oper1, regs.byteregs[regal]);

  3297.                 break;

  3298. 

  3299.             case 0xEF:	/* EF OUT regdx eAX */

  3300.                 oper1 = regs.wordregs[regdx];

  3301.                 portout16 (oper1, regs.wordregs[regax]);

  3302.                 break;

  3303. 

  3304.             case 0xF0:	/* F0 LOCK */

  3305.                 break;

  3306. 

  3307.             case 0xF4:	/* F4 HLT */

  3308.                 hltstate = 1;

  3309.                 break;

  3310. 

  3311.             case 0xF5:	/* F5 CMC */

  3312.                 if (!cf) {

  3313.                         cf = 1;

  3314.                     }

  3315.                 else {

  3316.                         cf = 0;

  3317.                     }

  3318.                 break;

  3319. 

  3320.             case 0xF6:	/* F6 GRP3a Eb */

  3321.                 modregrm();

  3322.                 oper1b = readrm8 (rm);

  3323.                 op_grp3_8();

  3324.                 if ( (reg > 1) && (reg < 4) ) {

  3325.                         writerm8 (rm, res8);

  3326.                     }

  3327.                 break;

  3328. 

  3329.             case 0xF7:	/* F7 GRP3b Ev */

  3330.                 modregrm();

  3331.                 oper1 = readrm16 (rm);

  3332.                 op_grp3_16();

  3333.                 if ( (reg > 1) && (reg < 4) ) {

  3334.                         writerm16 (rm, res16);

  3335.                     }

  3336.                 break;

  3337. 

  3338.             case 0xF8:	/* F8 CLC */

  3339.                 cf = 0;

  3340.                 break;

  3341. 

  3342.             case 0xF9:	/* F9 STC */

  3343.                 cf = 1;

  3344.                 break;

  3345. 

  3346.             case 0xFA:	/* FA CLI */

  3347.                 ifl = 0;

  3348.                 break;

  3349. 

  3350.             case 0xFB:	/* FB STI */

  3351.                 ifl = 1;

  3352.                 break;

  3353. 

  3354.             case 0xFC:	/* FC CLD */

  3355.                 df = 0;

  3356.                 break;

  3357. 

  3358.             case 0xFD:	/* FD STD */

  3359.                 df = 1;

  3360.                 break;

  3361. 

  3362.             case 0xFE:	/* FE GRP4 Eb */

  3363.                 modregrm();

  3364.                 oper1b = readrm8 (rm);

  3365.                 oper2b = 1;

  3366.                 if (!reg) {

  3367.                         tempcf = cf;

  3368.                         res8 = oper1b + oper2b;

  3369.                         flag_add8 (oper1b, oper2b);

  3370.                         cf = tempcf;

  3371.                         writerm8 (rm, res8);

  3372.                     }

  3373.                 else {

  3374.                         tempcf = cf;

  3375.                         res8 = oper1b - oper2b;

  3376.                         flag_sub8 (oper1b, oper2b);

  3377.                         cf = tempcf;

  3378.                         writerm8 (rm, res8);

  3379.                     }

  3380.                 break;

  3381. 

  3382.             case 0xFF:	/* FF GRP5 Ev */

  3383.                 modregrm();

  3384.                 oper1 = readrm16 (rm);

  3385.                 op_grp5();

  3386.                 break;

  3387. 

  3388.             default:

  3389. #ifdef CPU_ALLOW_ILLEGAL_OP_EXCEPTION

  3390.                 intcall86 (6); /* trip invalid opcode exception (this occurs on the 80186+, 8086/8088 CPUs treat them as NOPs. */

  3391.                                /* technically they aren't exactly like NOPs in most cases, but for our pursoses, that's accurate enough. */

  3392. #endif

  3393.                 break;

  3394.         }

  3395.     }

  3396. }

  3397. 

  3398. void reset86() {

  3399. 	segregs[regcs] = 0;

  3400. 	ip = 0;

  3401. 	hltstate = 0;

  3402. }