2019-12-13 17:38:40 -05:00
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; Same thing as instr.asm, but for AVR instructions
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; *** Instructions table ***
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; List of mnemonic names separated by a null terminator. Their index in the
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; list is their ID. Unlike in zasm, not all mnemonics have constant associated
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; to it because it's generally not needed. This list is grouped by argument
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; categories, and then alphabetically. Categories are ordered so that the 8bit
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; opcodes come first, then the 16bit ones. 0xff ends the chain
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instrNames:
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2019-12-13 22:49:15 -05:00
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; Branching instructions. They are all shortcuts to BRBC/BRBS. Their respective
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; bits are listed in instrBRBits. These are not in alphabetical order, but
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; rather in "bit order". All "bit set" instructions first (10th bit clear), then
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; all "bit clear" ones (10th bit set). Inside this order, they're then in "sss"
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; order (bit number alias for BRBC/BRBS)
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.db "BRCS", 0
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.db "BREQ", 0
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.db "BRMI", 0
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.db "BRVS", 0
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.db "BRLT", 0
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.db "BRHS", 0
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.db "BRTS", 0
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.db "BRIE", 0
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.db "BRCC", 0
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.db "BRNE", 0
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.db "BRPL", 0
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.db "BRVC", 0
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.db "BRGE", 0
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.db "BRHC", 0
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.db "BRTC", 0
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.db "BRID", 0
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.equ I_BRBS 16
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.db "BRBS", 0
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.db "BRBC", 0
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2019-12-13 17:38:40 -05:00
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; Rd(5) + Rr(5)
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2019-12-13 22:49:15 -05:00
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.equ I_ADC 18
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2019-12-13 17:38:40 -05:00
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.db "ADC", 0
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.db "ADD", 0
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.db "AND", 0
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.db "CLR", 0
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.db "CP", 0
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.db "CPC", 0
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.db "CPSE", 0
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.db "EOR", 0
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.db "MOV", 0
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.db "MUL", 0
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.db "OR", 0
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.db "SBC", 0
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.db "SUB", 0
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; no arg
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2019-12-13 22:49:15 -05:00
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.equ I_BREAK 31
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2019-12-13 17:38:40 -05:00
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.db "BREAK", 0
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.db "CLC", 0
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.db "CLH", 0
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.db "CLI", 0
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.db "CLN", 0
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.db "CLS", 0
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.db "CLT", 0
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.db "CLV", 0
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.db "CLZ", 0
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.db "EICALL", 0
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.db "EIJMP", 0
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.db "ICALL", 0
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.db "IJMP", 0
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.db "NOP", 0
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.db "RET", 0
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.db "RETI", 0
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.db "SEC", 0
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.db "SEH", 0
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.db "SEI", 0
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.db "SEN", 0
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.db "SES", 0
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.db "SET", 0
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.db "SEV", 0
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.db "SEZ", 0
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.db "SLEEP", 0
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.db "WDR", 0
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; Rd(5)
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2019-12-13 22:49:15 -05:00
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.equ I_ASR 57
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2019-12-13 17:38:40 -05:00
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.db "ASR", 0
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.db "COM", 0
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.db "DEC", 0
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.db "INC", 0
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.db "LAC", 0
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.db "LAS", 0
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.db "LAT", 0
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.db "LSR", 0
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.db "NEG", 0
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.db "POP", 0
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.db "PUSH", 0
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.db "ROR", 0
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.db "SWAP", 0
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.db "XCH", 0
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.db 0xff
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; 8-bit constant masks associated with each instruction. In the same order as
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; in instrNames
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instrUpMasks1:
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; Rd(5) + Rd(5): XXXXXXrd ddddrrrr
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.db 0b00011100 ; ADC
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.db 0b00001100 ; ADD
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.db 0b00100000 ; AND
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.db 0b00100100 ; CLR
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.db 0b00010100 ; CP
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.db 0b00000100 ; CPC
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.db 0b00010000 ; CPSE
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.db 0b00100100 ; EOR
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.db 0b00101100 ; MOV
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.db 0b10011100 ; MUL
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.db 0b00101000 ; OR
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.db 0b00001000 ; SBC
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.db 0b00011000 ; SUB
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; 16-bit constant masks associated with each instruction. In the same order as
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; in instrNames
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instrUpMasks2:
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; no arg
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.db 0b10010101, 0b10011000 ; BREAK
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.db 0b10010100, 0b10001000 ; CLC
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.db 0b10010100, 0b11011000 ; CLH
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.db 0b10010100, 0b11111000 ; CLI
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.db 0b10010100, 0b10101000 ; CLN
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.db 0b10010100, 0b11001000 ; CLS
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.db 0b10010100, 0b11101000 ; CLT
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.db 0b10010100, 0b10111000 ; CLV
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.db 0b10010100, 0b10011000 ; CLZ
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.db 0b10010101, 0b00011001 ; EICALL
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.db 0b10010100, 0b00011001 ; EIJMP
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.db 0b10010101, 0b00001001 ; ICALL
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.db 0b10010100, 0b00001001 ; IJMP
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.db 0b00000000, 0b00000000 ; NOP
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.db 0b10010101, 0b00001000 ; RET
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.db 0b10010101, 0b00011000 ; RETI
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.db 0b10010100, 0b00001000 ; SEC
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.db 0b10010100, 0b01011000 ; SEH
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.db 0b10010100, 0b01111000 ; SEI
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.db 0b10010100, 0b00101000 ; SEN
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.db 0b10010100, 0b01001000 ; SES
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.db 0b10010100, 0b01101000 ; SET
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.db 0b10010100, 0b00111000 ; SEV
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.db 0b10010100, 0b00011000 ; SEZ
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.db 0b10010101, 0b10001000 ; SLEEP
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.db 0b10010101, 0b10101000 ; WDR
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; Rd(5): XXXXXXXd ddddXXXX
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.db 0b10010100, 0b00000101 ; ASR
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.db 0b10010100, 0b00000000 ; COM
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.db 0b10010100, 0b00001010 ; DEC
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.db 0b10010100, 0b00000011 ; INC
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.db 0b10010010, 0b00000110 ; LAC
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.db 0b10010010, 0b00000101 ; LAS
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.db 0b10010010, 0b00000111 ; LAT
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.db 0b10010100, 0b00000110 ; LSR
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.db 0b10010100, 0b00000001 ; NEG
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.db 0b10010000, 0b00001111 ; POP
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.db 0b10010010, 0b00001111 ; PUSH
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.db 0b10010100, 0b00000111 ; ROR
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.db 0b10010100, 0b00000010 ; SWAP
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.db 0b10010010, 0b00000100 ; XCH
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2019-12-13 22:49:15 -05:00
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instrBRBits:
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; 1st bit is 3rd bit of MSB and the other 3 are the lower bits of LSB
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.db 0b0000 ; BRCS
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.db 0b0001 ; BREQ
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.db 0b0010 ; BRMI
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.db 0b0011 ; BRVS
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.db 0b0100 ; BRLT
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.db 0b0101 ; BRHS
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.db 0b0110 ; BRTS
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.db 0b0111 ; BRIE
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.db 0b1000 ; BRCC
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.db 0b1001 ; BRNE
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.db 0b1010 ; BRPL
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.db 0b1011 ; BRVC
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.db 0b1100 ; BRGE
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.db 0b1101 ; BRHC
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.db 0b1110 ; BRTC
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.db 0b1111 ; BRID
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2019-12-13 17:38:40 -05:00
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; Same signature as getInstID in instr.asm
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; Reads string in (HL) and returns the corresponding ID (I_*) in A. Sets Z if
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; there's a match.
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getInstID:
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push bc
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push hl
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push de
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ex de, hl ; DE makes a better needle
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; haystack. -1 because we inc HL at the beginning of the loop
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ld hl, instrNames-1
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ld b, 0xff ; index counter
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.loop:
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inc b
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inc hl
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ld a, (hl)
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inc a ; check if 0xff
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jr z, .notFound
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call strcmpIN
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jr nz, .loop
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; found!
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ld a, b ; index
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cp a ; ensure Z
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.end:
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pop de
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pop hl
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pop bc
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ret
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.notFound:
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dec a ; unset Z
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jr .end
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; Same signature as parseInstruction in instr.asm
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; Parse instruction specified in A (I_* const) with args in I/O and write
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; resulting opcode(s) in I/O.
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; Sets Z on success. On error, A contains an error code (ERR_*)
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parseInstruction:
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; BC, during .spit, is ORred to the spitted opcode.
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ld bc, 0
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cp I_ADC
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jp c, .BR
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cp I_BREAK
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jr c, .spitRd5Rr5
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cp I_ASR
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jr c, .spitNoArg
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; spitRd5
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ld d, a ; save A for later
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call .readR5
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ret nz
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call .placeRd
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ld a, d ; restore A
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; continue to .spitNoArg
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.spitNoArg:
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call .getUp2
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jr .spit
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.spitRd5Rr5:
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ld d, a ; save A for later
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call .readR5
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ret nz
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call .placeRd
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call readComma
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call .readR5
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ret nz
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push af ; --> lvl 1
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; let's start with the 4 lower bits
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and 0xf
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or c
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; We now have our LSB in A. Let's spit it now.
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call ioPutB
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pop af ; <-- lvl 1
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; and now that last high bit, currently bit 4, which must become bit 1
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and 0b00010000
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rra \ rra \ rra
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or b
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ld b, a
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ld a, d ; restore A
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2019-12-13 22:49:15 -05:00
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call .getUp1
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2019-12-13 17:38:40 -05:00
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; now that's our MSB
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jr .spitMSB
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.spit:
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; LSB is spit *before* MSB
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inc hl
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ld a, (hl)
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or c
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call ioPutB
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dec hl
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.spitMSB:
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ld a, (hl)
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or b
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call ioPutB
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xor a ; ensure Z, set success
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ret
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2019-12-13 22:49:15 -05:00
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; Spit a branching mnemonic.
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.BR:
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; While we have our index in A, let's settle B straight: Our base
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; upcode is 0b11110000 for "bit set" types and 0b11110100 for "bit
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; clear" types. However, we'll have 2 left shift operation done on B
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; later on, so we need those bits shifted right.
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ld b, 0b111100
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cp I_BRBS
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jr z, .rdBRBS
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jr nc, .rdBRBC
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; We have an alias. Our "sss" value is index & 0b111
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; Before we get rid of that 3rd bit, let's see, is it set? if yes, we'll
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; want to increase B
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bit 3, a
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jr z, .skip1 ; 3rd bit unset
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inc b
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.skip1:
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and 0b111
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ld c, a
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.spitBR2:
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call readWord
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ret nz
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call parseExpr
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ret nz
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; IX contains an absolute value. Turn this into a -64/+63 relative
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; value by subtracting PC from it. However, before we do that, let's
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; add 0x7f to it, which we'll remove later. This will simplify bounds
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; checks. (we use 7f instead of 3f because we deal in bytes here, not
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; in words)
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push ix \ pop hl
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ld de, 0x7f
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add hl, de ; Carry cleared
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ex de, hl
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call zasmGetPC ; --> HL
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; The relative value is actually not relative to current PC, but to
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; PC after the execution of this branching op. Increase HL by 2.
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inc hl \ inc hl
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ex de, hl
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sbc hl, de
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jp c, unsetZ ; Carry? error
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ld de, 0x7f
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sbc hl, de
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; We're within bounds! However, our value in L is the number of
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; relative *bytes*. The value we put there is the number of words.
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; Thefore, relevant bits are 7:1
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ld a, l
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sla a \ rl b
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sla a \ rl b
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; k is now shifted by 3, two of those bits being in B. Let's OR A and
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; C and we have our LSB ready to go.
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or c
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call ioPutB
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; Good! MSB now. B is already good to go.
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ld a, b
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jp ioPutB
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.rdBRBC:
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|
; In addition to reading "sss", we also need to inc B so that our base
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; upcode becomes 0b111101
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inc b
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.rdBRBS:
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|
call readWord
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ret nz
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|
|
call parseExpr
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|
|
|
ld a, 7
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|
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|
call .IX2A
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|
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|
ret nz
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|
|
ld c, a
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|
|
|
call readComma
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|
ret nz
|
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|
jr .spitBR2
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|
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|
2019-12-13 17:38:40 -05:00
|
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|
; local routines
|
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|
|
|
; place number in A in BC at position .......d dddd....
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|
|
|
; BC is assumed to be 0
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|
|
|
|
.placeRd:
|
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|
|
sla a \ rla \ rla \ rla ; last RLA might set carry
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|
|
|
rl b
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|
|
|
|
ld c, a
|
|
|
|
|
ret
|
2019-12-13 22:49:15 -05:00
|
|
|
|
|
|
|
|
; Fetch a 8-bit upcode specified by instr index in A and set that upcode in HL
|
|
|
|
|
.getUp1:
|
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|
|
|
sub I_ADC
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|
|
|
ld hl, instrUpMasks1
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|
|
|
|
jp addHL
|
|
|
|
|
|
2019-12-13 17:38:40 -05:00
|
|
|
; Fetch a 16-bit upcode specified by instr index in A and set that upcode in HL
|
|
|
|
|
.getUp2:
|
|
|
|
|
sub I_BREAK
|
|
|
|
|
sla a ; A * 2
|
|
|
|
|
ld hl, instrUpMasks2
|
|
|
|
|
jp addHL
|
|
|
|
|
|
|
|
|
|
; read a rXX argument and return register number in A.
|
|
|
|
|
; Set Z for success.
|
|
|
|
|
.readR5:
|
|
|
|
|
call readWord
|
|
|
|
|
ld a, (hl)
|
|
|
|
|
call upcase
|
|
|
|
|
cp 'R'
|
|
|
|
|
ret nz ; not a register
|
|
|
|
|
inc hl
|
|
|
|
|
call parseDecimal
|
|
|
|
|
ret nz
|
2019-12-13 22:49:15 -05:00
|
|
|
ld a, 31
|
|
|
|
|
jr .IX2A
|
|
|
|
|
|
|
|
|
|
; Put IX's LSB into A and, additionally, ensure that the new value is <=
|
|
|
|
|
; than what was previously in A.
|
|
|
|
|
; Z for success.
|
|
|
|
|
.IX2A:
|
2019-12-13 17:38:40 -05:00
|
|
|
push ix \ pop hl
|
2019-12-13 22:49:15 -05:00
|
|
|
cp l
|
|
|
|
|
jp c, unsetZ ; A < L
|
2019-12-13 17:38:40 -05:00
|
|
|
ld a, h
|
|
|
|
|
or a
|
|
|
|
|
ret nz ; should be zero
|
|
|
|
|
ld a, l
|
2019-12-13 22:49:15 -05:00
|
|
|
; Z set from "or a"
|
2019-12-13 17:38:40 -05:00
|
|
|
ret
|
