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@@ -1,9 +1,16 @@ |
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This is because there's bitwise ORing involved in the creation |
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of the final opcode, which makes z80a's approach impractical. |
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This assembler works very much like Z80 assembler (B200) so |
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refer to this documentation first. Here, we document specifici- |
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ties. |
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This makes labelling a bit different too. Instead of expecting |
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label words after the naked branching op, we rather have label |
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words expecting branching wordref as an argument. Examples: |
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All mnemonics in AVR have a single signature. Therefore, we |
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don't need any "argtype" suffixes. |
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L2 ' BRTS FLBL! ( branch forward to L2 ) |
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L1 ' RJMP LBL, ( branch backward to L1 ) |
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Registers are referred to with consts R0-R31. There is |
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X, Y, Z, X+, Y+, Z+, X-, Y-, Z- for appropriate ops (LD, ST). |
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XL, XH, YL, YH, ZL, ZH are simple aliases to R26-R31. |
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Branching works differently. Instead of expecting a byte to be |
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written after the naked op, branching words expect a displace- |
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ment argument. |
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(cont.) |