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; Use this as a debug companion to at28wr. This simply dumps, TTY-escaped, the |
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; contents of the AT28. |
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; |
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; TODO: not always, but sometimes, the output starts with a spurious 0xFF. But |
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; otherwise, the rest of the contents is good, albeit offset by 1 (that is, the |
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; byte after the spurious 0xFF is the contents at addr 0). Weird, to fix. |
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.include "m328Pdef.inc" |
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; *** Pins *** |
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.equ SRCP = PORTB2 |
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.equ SRDS = PORTB1 |
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.equ FLWE = PORTB3 |
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.equ FLOE = PORTB4 |
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.equ FLCE = PORTB5 ; WARNING: same as LED |
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; *** Consts *** |
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.equ BAUD_PRESCALE = 103 ; 9600 bauds at 16mhz |
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rjmp main |
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; *** Code *** |
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; Sends char in r20 to UART |
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; Perform TTY-escape transparently. |
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uartwr: |
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lds r16, UCSR0A |
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sbrs r16, UDRE0 ; wait until send buffer is empty |
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rjmp uartwr |
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; should we escape? |
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cpi r20, 0x21 |
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brsh uartwr_0 ; r20 >= 0x21, skip |
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; escape |
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ori r20, 0x80 |
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ldi r16, 0x20 |
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sts UDR0, r16 |
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rjmp uartwr |
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uartwr_0: |
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sts UDR0, r20 |
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ret |
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; send r23 to addr shift register. |
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; We send highest bits first so that Q7 is the MSB and Q0 is the LSB |
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sendaddr: |
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ldi r16, 8 ; we will loop 8 times |
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cbi PORTB, SRDS |
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sbrc r23, 7 ; if latest bit isn't cleared, set SER_DP high |
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sbi PORTB, SRDS |
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; toggle SRCP, not waiting between pulses. The CD74AC164 at 5V has a |
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; 5.9ns CP min pulse width. We can't match that at 16mhz. No need to |
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; wait. |
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cbi PORTB, SRCP |
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sbi PORTB, SRCP |
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lsl r23 ; shift our data left |
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dec r16 |
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brne sendaddr+1 ; not zero yet? loop! (+1 to avoid reset) |
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ret |
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; push r20 to the rom and increase the memory counter |
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nextaddr: |
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; first, set up addr |
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mov r23, r21 |
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rcall sendaddr |
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mov r23, r22 |
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rcall sendaddr |
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inc r22 |
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brne nextaddr_0 ; no overflow? skip |
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inc r21 |
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nextaddr_0: |
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ret |
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; read EEPROM's I/O7:0 through PD7:2 and PB1:0 into r20 |
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readdata: |
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cbi PORTB, FLCE |
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cbi PORTB, FLOE |
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nop ; 70ns max delay on at28 |
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nop |
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nop |
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nop |
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; read bits 7:2 |
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in r20, PIND |
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andi r20, 0xfc |
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; read bits 1:0 |
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in r16, PINB |
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andi r16, 0x03 |
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or r20, r16 |
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sbi PORTB, FLOE |
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sbi PORTB, FLCE |
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ret |
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; Set PD7:2 and PB1:0 to output |
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ioout: |
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ldi r16, 0xfc ; PD7:2 |
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out DDRD, r16 |
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ldi r16, 0x3f ; PB5:0 (CP, WE, OE and CE too) |
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out DDRB, r16 |
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ret |
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; Set PD7:2 and PB1:0 to input |
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ioin: |
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ldi r16, 0x03 ; PD7:2 |
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out DDRD, r16 |
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ldi r16, 0x3c ; PB1:0 |
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out DDRB, r16 |
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ret |
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main: |
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ldi r16, low(RAMEND) |
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out SPL, r16 |
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ldi r16, high(RAMEND) |
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out SPH, r16 |
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; We begin with WE and OE disabled (high), but CE stays enabled (low) |
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; the whole time. |
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sbi PORTB, FLWE |
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sbi PORTB, FLOE |
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sbi PORTB, FLCE |
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; Clear counters and flags |
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clr r21 |
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clr r22 |
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; Setup UART |
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ldi R16, low(BAUD_PRESCALE) |
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sts UBRR0L, r16 |
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ldi r16, high(BAUD_PRESCALE) |
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sts UBRR0H, r16 |
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ldi r16, (1<<TXEN0) |
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sts UCSR0B, r16 |
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loop: |
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rcall ioout |
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rcall nextaddr |
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rcall ioin |
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rcall readdata |
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rcall uartwr |
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rjmp loop |
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