trs80: adapt recipe to single stage xcomp
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8a58449776
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3
blk/490
3
blk/490
@ -4,8 +4,7 @@ Support code for the TRS-80 recipe. Contains drivers for the
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keyboard, video and floppy. At the moment, they are thin layer
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over the drivers provided by TRSDOS' SVC.
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Load the Z80 words with "492 LOAD" and the high level part
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with "498 LOAD".
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Load with "492 LOAD".
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There is also the RECV program at B502 and the XCOMP unit at
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B504
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blk/499
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@ -1,4 +1,4 @@
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: _err ABORT" FDerr" ;
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: _err LIT" FDerr" ERR ;
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: _cylsec ( sec -- cs, return sector/cylinder for given secid )
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( 4 256b sectors per block, 10 sec per cyl, 40 cyl max )
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10 /MOD ( sec cyl )
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@ -2,6 +2,6 @@
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: FD! ['] @WRSEC SWAP FD@! ;
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: FD$ ['] FD@ BLK@* ! ['] FD! BLK!* ! ;
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: _err ABORT" *CLerr" ;
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: _err LIT" *CLerr" ERR ;
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: *CL< 0 BEGIN DROP 0x0238 @GET UNTIL ;
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: *CL> 0x0238 @PUT NOT IF _err THEN ;
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@ -1,4 +1,4 @@
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TARGET = stage1.bin
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TARGET = os.bin
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EDIR = ../../emul
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STAGE = $(EDIR)/stage
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@ -67,10 +67,10 @@ kind of reception! You're gonna feel real badass about it too...
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* `_` is `CLEAR+ENTER`.
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## Building the stage 1
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## Building the binary
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You can start the process by building the stage 1 binary. Running `make` in
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this folder will yield a `stage1.bin` file. You'll need it later.
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You can build the binary to send to the TRS-80 with `make`, which will yield
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`os.bin`. You'll need it later.
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## Testing serial communication
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@ -7,14 +7,13 @@ RS_ADDR 0x80 - CONSTANT RAMSTART
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0x3000 BIN( !
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282 LOAD ( boot.z80 )
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492 LOAD ( trs80.z80 )
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393 LOAD ( xcomp core low )
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492 LOAD ( trs80 )
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420 LOAD ( xcomp core high )
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(entry) _
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( Update LATEST )
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PC ORG @ 8 + !
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," CURRENT @ HERE ! "
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499 500 XPACKR ( trs80.fs )
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( 0x0a == NLPTR. TRS-80 wants CR-only newlines )
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," : _ ['] CR 0x0a RAM+ ! BLK$ FD$ (ok) RDLN$ ; _ "
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ORG @ 256 /MOD 2 PC! 2 PC!
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