46676547d9
AVR chips often run at less than z80's system clock. This means that our SPI relay needs to have its own clock to properly communicate with it. This means that the delay between OUT and IN can't be hardcoded to 2 NOPs anymore. It needs to be configurable.
13 lines
217 B
Plaintext
13 lines
217 B
Plaintext
CODE (spix) ( n -- n )
|
|
HL POP,
|
|
chkPS,
|
|
A L LDrr,
|
|
SPI_DATA OUTiA,
|
|
SPI_DELAY
|
|
SPI_DATA INAi,
|
|
L A LDrr,
|
|
HL PUSH,
|
|
;CODE
|
|
CODE (spie) SPI_CSLOW OUTiA, ;CODE
|
|
CODE (spid) SPI_CSHIGH OUTiA, ;CODE
|