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sprite animation testing
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testingAnimation/inc/hardware.inc

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  1. ;*

  2. ;* Gameboy Hardware definitions

  3. ;*

  4. ;* Based on Jones' hardware.inc

  5. ;* And based on Carsten Sorensen's ideas.

  6. ;*

  7. ;* Rev 1.1 - 15-Jul-97 : Added define check

  8. ;* Rev 1.2 - 18-Jul-97 : Added revision check macro

  9. ;* Rev 1.3 - 19-Jul-97 : Modified for RGBASM V1.05

  10. ;* Rev 1.4 - 27-Jul-97 : Modified for new subroutine prefixes

  11. ;* Rev 1.5 - 15-Aug-97 : Added _HRAM, PAD, CART defines

  12. ;*                     :  and Nintendo Logo

  13. ;* Rev 1.6 - 30-Nov-97 : Added rDIV, rTIMA, rTMA, & rTAC

  14. ;* Rev 1.7 - 31-Jan-98 : Added _SCRN0, _SCRN1

  15. ;* Rev 1.8 - 15-Feb-98 : Added rSB, rSC

  16. ;* Rev 1.9 - 16-Feb-98 : Converted I/O registers to $FFXX format

  17. ;* Rev 2.0 -           : Added GBC registers

  18. ;* Rev 2.1 -           : Added MBC5 & cart RAM enable/disable defines

  19. ;* Rev 2.2 -           : Fixed NR42,NR43, & NR44 equates

  20. ;* Rev 2.3 -           : Fixed incorrect _HRAM equate

  21. ;* Rev 2.4 - 27-Apr-13 : Added some cart defines (AntonioND)

  22. ;* Rev 2.5 - 03-May-15 : Fixed format (AntonioND)

  23. ;* Rev 2.6 - 09-Apr-16 : Added GBC OAM and cart defines (AntonioND)

  24. ;* Rev 2.7 - 19-Jan-19 : Added rPCMXX (ISSOtm)

  25. ;* Rev 2.8 - 03-Feb-19 : Added audio registers flags (Álvaro Cuesta)

  26. 

  27. ; If all of these are already defined, don't do it again.

  28. 

  29.     IF !DEF(HARDWARE_INC)

  30. HARDWARE_INC SET 1

  31. 

  32. rev_Check_hardware_inc : MACRO

  33. ;NOTE: REVISION NUMBER CHANGES MUST BE ADDED

  34. ;TO SECOND PARAMETER IN FOLLOWING LINE.

  35.     IF  \1 > 2.8 ;PUT REVISION NUMBER HERE

  36.         WARN    "Version \1 or later of 'hardware.inc' is required."

  37.     ENDC

  38. ENDM

  39. 

  40. _HW          EQU $FF00

  41. 

  42. _VRAM        EQU $8000 ; $8000->$9FFF

  43. _BGTILES     EQU $9000

  44. _SCRN0       EQU $9800 ; $9800->$9BFF

  45. _SCRN0_END   EQU $9BFF

  46. _SCRN1       EQU $9C00 ; $9C00->$9FFF

  47. _SRAM        EQU $A000 ; $A000->$BFFF

  48. _RAM         EQU $C000 ; $C000->$DFFF

  49. _OAMRAM      EQU $FE00 ; $FE00->$FE9F

  50. _AUD3WAVERAM EQU $FF30 ; $FF30->$FF3F

  51. _HRAM        EQU $FF80 ; $FF80->$FFFE

  52. 

  53. ; *** MBC5 Equates ***

  54. 

  55. rRAMG        EQU $0000 ; $0000->$1fff

  56. rROMB0       EQU $2000 ; $2000->$2fff

  57. rROMB1       EQU $3000 ; $3000->$3fff - If more than 256 ROM banks are present.

  58. rRAMB        EQU $4000 ; $4000->$5fff - Bit 3 enables rumble (if present)

  59. 

  60. 

  61. ; --

  62. ; -- OAM flags

  63. ; --

  64. 

  65. OAMF_PRI        EQU %10000000 ; Priority

  66. OAMF_YFLIP      EQU %01000000 ; Y flip

  67. OAMF_XFLIP      EQU %00100000 ; X flip

  68. OAMF_PAL0       EQU %00000000 ; Palette number; 0,1 (DMG)

  69. OAMF_PAL1       EQU %00010000 ; Palette number; 0,1 (DMG)

  70. OAMF_BANK0      EQU %00000000 ; Bank number; 0,1 (GBC)

  71. OAMF_BANK1      EQU %00001000 ; Bank number; 0,1 (GBC)

  72. 

  73. OAMF_PALMASK    EQU %00000111 ; Palette (GBC)

  74. 

  75. OAMB_PRI        EQU 7 ; Priority 

  76. OAMB_YFLIP      EQU 6 ; Y flip 

  77. OAMB_XFLIP      EQU 5 ; X flip 

  78. OAMB_PAL1       EQU 4 ; Palette number; 0,1 (DMG) 

  79. OAMB_BANK1      EQU 3 ; Bank number; 0,1 (GBC) 

  80. 

  81. 

  82. ;***************************************************************************

  83. ;*

  84. ;* Custom registers

  85. ;*

  86. ;***************************************************************************

  87. 

  88. ; --

  89. ; -- P1 ($FF00)

  90. ; -- Register for reading joy pad info.    (R/W)

  91. ; --

  92. rP1 EQU $FF00

  93. 

  94. P1F_5 EQU %00100000 ; P15 out port

  95. P1F_4 EQU %00010000 ; P14 out port

  96. P1F_3 EQU %00001000 ; P13 in port

  97. P1F_2 EQU %00000100 ; P12 in port

  98. P1F_1 EQU %00000010 ; P11 in port

  99. P1F_0 EQU %00000001 ; P10 in port

  100. 

  101. ; --

  102. ; -- SB ($FF01)

  103. ; -- Serial Transfer Data (R/W)

  104. ; --

  105. rSB EQU $FF01

  106. 

  107. ; --

  108. ; -- SC ($FF02)

  109. ; -- Serial I/O Control (R/W)

  110. ; --

  111. rSC EQU $FF02

  112. 

  113. ; --

  114. ; -- DIV ($FF04)

  115. ; -- Divider register (R/W)

  116. ; --

  117. rDIV EQU $FF04

  118. 

  119. 

  120. ; --

  121. ; -- TIMA ($FF05)

  122. ; -- Timer counter (R/W)

  123. ; --

  124. rTIMA EQU $FF05

  125. 

  126. 

  127. ; --

  128. ; -- TMA ($FF06)

  129. ; -- Timer modulo (R/W)

  130. ; --

  131. rTMA EQU $FF06

  132. 

  133. 

  134. ; --

  135. ; -- TAC ($FF07)

  136. ; -- Timer control (R/W)

  137. ; --

  138. rTAC EQU $FF07

  139. 

  140. TACF_START  EQU %00000100

  141. TACF_STOP   EQU %00000000

  142. TACF_4KHZ   EQU %00000000

  143. TACF_16KHZ  EQU %00000011

  144. TACF_65KHZ  EQU %00000010

  145. TACF_262KHZ EQU %00000001

  146. 

  147. ; --

  148. ; -- IF ($FF0F)

  149. ; -- Interrupt Flag (R/W)

  150. ; --

  151. rIF EQU $FF0F

  152. 

  153. ; --

  154. ; -- LCDC ($FF40)

  155. ; -- LCD Control (R/W)

  156. ; --

  157. rLCDC EQU $FF40

  158. 

  159. LCDCF_OFF     EQU %00000000 ; LCD Control Operation

  160. LCDCF_ON      EQU %10000000 ; LCD Control Operation

  161. LCDCF_WIN9800 EQU %00000000 ; Window Tile Map Display Select

  162. LCDCF_WIN9C00 EQU %01000000 ; Window Tile Map Display Select

  163. LCDCF_WINOFF  EQU %00000000 ; Window Display

  164. LCDCF_WINON   EQU %00100000 ; Window Display

  165. LCDCF_BG8800  EQU %00000000 ; BG & Window Tile Data Select

  166. LCDCF_BG8000  EQU %00010000 ; BG & Window Tile Data Select

  167. LCDCF_BG9800  EQU %00000000 ; BG Tile Map Display Select

  168. LCDCF_BG9C00  EQU %00001000 ; BG Tile Map Display Select

  169. LCDCF_OBJ8    EQU %00000000 ; OBJ Construction

  170. LCDCF_OBJ16   EQU %00000100 ; OBJ Construction

  171. LCDCF_OBJOFF  EQU %00000000 ; OBJ Display

  172. LCDCF_OBJON   EQU %00000010 ; OBJ Display

  173. LCDCF_BGOFF   EQU %00000000 ; BG Display

  174. LCDCF_BGON    EQU %00000001 ; BG Display

  175. ; "Window Character Data Select" follows BG

  176. 

  177. 

  178. ; --

  179. ; -- STAT ($FF41)

  180. ; -- LCDC Status   (R/W)

  181. ; --

  182. rSTAT EQU $FF41

  183. 

  184. STATF_LYC     EQU  %01000000 ; LYCEQULY Coincidence (Selectable)

  185. STATF_MODE10  EQU  %00100000 ; Mode 10

  186. STATF_MODE01  EQU  %00010000 ; Mode 01 (V-Blank)

  187. STATF_MODE00  EQU  %00001000 ; Mode 00 (H-Blank)

  188. STATF_LYCF    EQU  %00000100 ; Coincidence Flag

  189. STATF_HB      EQU  %00000000 ; H-Blank

  190. STATF_VB      EQU  %00000001 ; V-Blank

  191. STATF_OAM     EQU  %00000010 ; OAM-RAM is used by system

  192. STATF_LCD     EQU  %00000011 ; Both OAM and VRAM used by system

  193. STATF_BUSY    EQU  %00000010 ; When set, VRAM access is unsafe

  194. 

  195. 

  196. ; --

  197. ; -- SCY ($FF42)

  198. ; -- Scroll Y (R/W)

  199. ; --

  200. rSCY EQU $FF42

  201. 

  202. 

  203. ; --

  204. ; -- SCY ($FF43)

  205. ; -- Scroll X (R/W)

  206. ; --

  207. rSCX EQU $FF43

  208. 

  209. 

  210. ; --

  211. ; -- LY ($FF44)

  212. ; -- LCDC Y-Coordinate (R)

  213. ; --

  214. ; -- Values range from 0->153. 144->153 is the VBlank period.

  215. ; --

  216. rLY EQU $FF44

  217. 

  218. 

  219. ; --

  220. ; -- LYC ($FF45)

  221. ; -- LY Compare (R/W)

  222. ; --

  223. ; -- When LYEQUEQULYC, STATF_LYCF will be set in STAT

  224. ; --

  225. rLYC EQU $FF45

  226. 

  227. 

  228. ; --

  229. ; -- DMA ($FF46)

  230. ; -- DMA Transfer and Start Address (W)

  231. ; --

  232. rDMA EQU $FF46

  233. 

  234. 

  235. ; --

  236. ; -- BGP ($FF47)

  237. ; -- BG Palette Data (W)

  238. ; --

  239. ; -- Bit 7-6 - Intensity for %11

  240. ; -- Bit 5-4 - Intensity for %10

  241. ; -- Bit 3-2 - Intensity for %01

  242. ; -- Bit 1-0 - Intensity for %00

  243. ; --

  244. rBGP EQU $FF47

  245. 

  246. 

  247. ; --

  248. ; -- OBP0 ($FF48)

  249. ; -- Object Palette 0 Data (W)

  250. ; --

  251. ; -- See BGP for info

  252. ; --

  253. rOBP0 EQU $FF48

  254. 

  255. 

  256. ; --

  257. ; -- OBP1 ($FF49)

  258. ; -- Object Palette 1 Data (W)

  259. ; --

  260. ; -- See BGP for info

  261. ; --

  262. rOBP1 EQU $FF49

  263. 

  264. 

  265. ; --

  266. ; -- WY ($FF4A)

  267. ; -- Window Y Position (R/W)

  268. ; --

  269. ; -- 0 <EQU WY <EQU 143

  270. ; --

  271. rWY EQU $FF4A

  272. 

  273. 

  274. ; --

  275. ; -- WX ($FF4B)

  276. ; -- Window X Position (R/W)

  277. ; --

  278. ; -- 7 <EQU WX <EQU 166

  279. ; --

  280. rWX EQU $FF4B

  281. 

  282. 

  283. ; --

  284. ; -- KEY 1 ($FF4D)

  285. ; -- Select CPU Speed (R/W)

  286. ; --

  287. rKEY1 EQU $FF4D

  288. 

  289. 

  290. ; --

  291. ; -- VBK ($FF4F)

  292. ; -- Select Video RAM Bank (R/W)

  293. ; --

  294. rVBK EQU $FF4F

  295. 

  296. 

  297. ; --

  298. ; -- HDMA1 ($FF51)

  299. ; -- Horizontal Blanking, General Purpose DMA (W)

  300. ; --

  301. rHDMA1 EQU $FF51

  302. 

  303. 

  304. ; --

  305. ; -- HDMA2 ($FF52)

  306. ; -- Horizontal Blanking, General Purpose DMA (W)

  307. ; --

  308. rHDMA2 EQU $FF52

  309. 

  310. 

  311. ; --

  312. ; -- HDMA3 ($FF53)

  313. ; -- Horizontal Blanking, General Purpose DMA (W)

  314. ; --

  315. rHDMA3 EQU $FF53

  316. 

  317. 

  318. ; --

  319. ; -- HDMA4 ($FF54)

  320. ; -- Horizontal Blanking, General Purpose DMA (W)

  321. ; --

  322. rHDMA4 EQU $FF54

  323. 

  324. 

  325. ; --

  326. ; -- HDMA5 ($FF55)

  327. ; -- Horizontal Blanking, General Purpose DMA (R/W)

  328. ; --

  329. rHDMA5 EQU $FF55

  330. 

  331. 

  332. ; --

  333. ; -- RP ($FF56)

  334. ; -- Infrared Communications Port (R/W)

  335. ; --

  336. rRP EQU $FF56

  337. 

  338. 

  339. ; --

  340. ; -- BCPS ($FF68)

  341. ; -- Background Color Palette Specification (R/W)

  342. ; --

  343. rBCPS EQU $FF68

  344. 

  345. 

  346. ; --

  347. ; -- BCPD ($FF69)

  348. ; -- Background Color Palette Data (R/W)

  349. ; --

  350. rBCPD EQU $FF69

  351. 

  352. 

  353. ; --

  354. ; -- BCPS ($FF6A)

  355. ; -- Object Color Palette Specification (R/W)

  356. ; --

  357. rOCPS EQU $FF6A

  358. 

  359. 

  360. ; --

  361. ; -- BCPD ($FF6B)

  362. ; -- Object Color Palette Data (R/W)

  363. ; --

  364. rOCPD EQU $FF6B

  365. 

  366. 

  367. ; --

  368. ; -- SVBK ($FF4F)

  369. ; -- Select Main RAM Bank (R/W)

  370. ; --

  371. rSVBK EQU $FF70

  372. 

  373. 

  374. ; --

  375. ; -- IE ($FFFF)

  376. ; -- Interrupt Enable (R/W)

  377. ; --

  378. rIE EQU $FFFF

  379. 

  380. 

  381. IEF_HILO   EQU %00010000 ; Transition from High to Low of Pin number P10-P13

  382. IEF_SERIAL EQU %00001000 ; Serial I/O transfer end

  383. IEF_TIMER  EQU %00000100 ; Timer Overflow

  384. IEF_LCDC   EQU %00000010 ; LCDC (see STAT)

  385. IEF_VBLANK EQU %00000001 ; V-Blank

  386. 

  387. 

  388. 

  389. 

  390. ;***************************************************************************

  391. ;*

  392. ;* Sound control registers

  393. ;*

  394. ;***************************************************************************

  395. 

  396. ; --

  397. ; -- AUDVOL/NR50 ($FF24)

  398. ; -- Channel control / ON-OFF / Volume (R/W)

  399. ; --

  400. ; -- Bit 7   - Vin->SO2 ON/OFF (Vin??)

  401. ; -- Bit 6-4 - SO2 output level (volume) (# 0-7)

  402. ; -- Bit 3   - Vin->SO1 ON/OFF (Vin??)

  403. ; -- Bit 2-0 - SO1 output level (volume) (# 0-7)

  404. ; --

  405. rNR50 EQU $FF24

  406. rAUDVOL EQU rNR50

  407. 

  408. AUDVOL_VIN_LEFT  EQU %10000000 ; SO2

  409. AUDVOL_VIN_RIGHT EQU %00001000 ; SO1

  410. 

  411. 

  412. ; --

  413. ; -- AUDTERM/NR51 ($FF25)

  414. ; -- Selection of Sound output terminal (R/W)

  415. ; --

  416. ; -- Bit 7   - Output sound 4 to SO2 terminal

  417. ; -- Bit 6   - Output sound 3 to SO2 terminal

  418. ; -- Bit 5   - Output sound 2 to SO2 terminal

  419. ; -- Bit 4   - Output sound 1 to SO2 terminal

  420. ; -- Bit 3   - Output sound 4 to SO1 terminal

  421. ; -- Bit 2   - Output sound 3 to SO1 terminal

  422. ; -- Bit 1   - Output sound 2 to SO1 terminal

  423. ; -- Bit 0   - Output sound 0 to SO1 terminal

  424. ; --

  425. rNR51 EQU $FF25

  426. rAUDTERM EQU rNR51

  427. 

  428. ; SO2

  429. AUDTERM_4_LEFT  EQU %10000000

  430. AUDTERM_3_LEFT  EQU %01000000

  431. AUDTERM_2_LEFT  EQU %00100000

  432. AUDTERM_1_LEFT  EQU %00010000

  433. ; SO1

  434. AUDTERM_4_RIGHT EQU %00001000

  435. AUDTERM_3_RIGHT EQU %00000100

  436. AUDTERM_2_RIGHT EQU %00000010

  437. AUDTERM_1_RIGHT EQU %00000001

  438. 

  439. 

  440. ; --

  441. ; -- AUDENA/NR52 ($FF26)

  442. ; -- Sound on/off (R/W)

  443. ; --

  444. ; -- Bit 7   - All sound on/off (sets all audio regs to 0!)

  445. ; -- Bit 3   - Sound 4 ON flag (doesn't work!)

  446. ; -- Bit 2   - Sound 3 ON flag (doesn't work!)

  447. ; -- Bit 1   - Sound 2 ON flag (doesn't work!)

  448. ; -- Bit 0   - Sound 1 ON flag (doesn't work!)

  449. ; --

  450. rNR52 EQU $FF26

  451. rAUDENA EQU rNR52

  452. 

  453. AUDENA_ON    EQU %10000000

  454. AUDENA_OFF   EQU %00000000  ; sets all audio regs to 0!

  455. 

  456. 

  457. ;***************************************************************************

  458. ;*

  459. ;* SoundChannel #1 registers

  460. ;*

  461. ;***************************************************************************

  462. 

  463. ; --

  464. ; -- AUD1SWEEP/NR10 ($FF10)

  465. ; -- Sweep register (R/W)

  466. ; --

  467. ; -- Bit 6-4 - Sweep Time

  468. ; -- Bit 3   - Sweep Increase/Decrease

  469. ; --           0: Addition    (frequency increases???)

  470. ; --           1: Subtraction (frequency increases???)

  471. ; -- Bit 2-0 - Number of sweep shift (# 0-7)

  472. ; -- Sweep Time: (n*7.8ms)

  473. ; --

  474. rNR10 EQU $FF10

  475. rAUD1SWEEP EQU rNR10

  476. 

  477. AUD1SWEEP_UP   EQU %00000000

  478. AUD1SWEEP_DOWN EQU %00001000

  479. 

  480. 

  481. ; --

  482. ; -- AUD1LEN/NR11 ($FF11)

  483. ; -- Sound length/Wave pattern duty (R/W)

  484. ; --

  485. ; -- Bit 7-6 - Wave Pattern Duty (00:12.5% 01:25% 10:50% 11:75%)

  486. ; -- Bit 5-0 - Sound length data (# 0-63)

  487. ; --

  488. rNR11 EQU $FF11

  489. rAUD1LEN EQU rNR11

  490. 

  491. 

  492. ; --

  493. ; -- AUD1ENV/NR12 ($FF12)

  494. ; -- Envelope (R/W)

  495. ; --

  496. ; -- Bit 7-4 - Initial value of envelope

  497. ; -- Bit 3   - Envelope UP/DOWN

  498. ; --           0: Decrease

  499. ; --           1: Range of increase

  500. ; -- Bit 2-0 - Number of envelope sweep (# 0-7)

  501. ; --

  502. rNR12 EQU $FF12

  503. rAUD1ENV EQU rNR12

  504. 

  505. 

  506. ; --

  507. ; -- AUD1LOW/NR13 ($FF13)

  508. ; -- Frequency lo (W)

  509. ; --

  510. rNR13 EQU $FF13

  511. rAUD1LOW EQU rNR13

  512. 

  513. 

  514. ; --

  515. ; -- AUD1HIGH/NR14 ($FF14)

  516. ; -- Frequency hi (W)

  517. ; --

  518. ; -- Bit 7   - Initial (when set, sound restarts)

  519. ; -- Bit 6   - Counter/consecutive selection

  520. ; -- Bit 2-0 - Frequency's higher 3 bits

  521. ; --

  522. rNR14 EQU $FF14

  523. rAUD1HIGH EQU rNR14

  524. 

  525. 

  526. ;***************************************************************************

  527. ;*

  528. ;* SoundChannel #2 registers

  529. ;*

  530. ;***************************************************************************

  531. 

  532. ; --

  533. ; -- AUD2LEN/NR21 ($FF16)

  534. ; -- Sound Length; Wave Pattern Duty (R/W)

  535. ; --

  536. ; -- see AUD1LEN for info

  537. ; --

  538. rNR21 EQU $FF16

  539. rAUD2LEN EQU rNR21

  540. 

  541. 

  542. ; --

  543. ; -- AUD2ENV/NR22 ($FF17)

  544. ; -- Envelope (R/W)

  545. ; --

  546. ; -- see AUD1ENV for info

  547. ; --

  548. rNR22 EQU $FF17

  549. rAUD2ENV EQU rNR22

  550. 

  551. 

  552. ; --

  553. ; -- AUD2LOW/NR23 ($FF18)

  554. ; -- Frequency lo (W)

  555. ; --

  556. rNR23 EQU $FF18

  557. rAUD2LOW EQU rNR23

  558. 

  559. 

  560. ; --

  561. ; -- AUD2HIGH/NR24 ($FF19)

  562. ; -- Frequency hi (W)

  563. ; --

  564. ; -- see AUD1HIGH for info

  565. ; --

  566. rNR24 EQU $FF19

  567. rAUD2HIGH EQU rNR24

  568. 

  569. 

  570. ;***************************************************************************

  571. ;*

  572. ;* SoundChannel #3 registers

  573. ;*

  574. ;***************************************************************************

  575. 

  576. ; --

  577. ; -- AUD3ENA/NR30 ($FF1A)

  578. ; -- Sound on/off (R/W)

  579. ; --

  580. ; -- Bit 7   - Sound ON/OFF (1EQUON,0EQUOFF)

  581. ; --

  582. rNR30 EQU $FF1A

  583. rAUD3ENA EQU rNR30

  584. 

  585. 

  586. ; --

  587. ; -- AUD3LEN/NR31 ($FF1B)

  588. ; -- Sound length (R/W)

  589. ; --

  590. ; -- Bit 7-0 - Sound length

  591. ; --

  592. rNR31 EQU $FF1B

  593. rAUD3LEN EQU rNR31

  594. 

  595. 

  596. ; --

  597. ; -- AUD3LEVEL/NR32 ($FF1C)

  598. ; -- Select output level

  599. ; --

  600. ; -- Bit 6-5 - Select output level

  601. ; --           00: 0/1 (mute)

  602. ; --           01: 1/1

  603. ; --           10: 1/2

  604. ; --           11: 1/4

  605. ; --

  606. rNR32 EQU $FF1C

  607. rAUD3LEVEL EQU rNR32

  608. 

  609. 

  610. ; --

  611. ; -- AUD3LOW/NR33 ($FF1D)

  612. ; -- Frequency lo (W)

  613. ; --

  614. ; -- see AUD1LOW for info

  615. ; --

  616. rNR33 EQU $FF1D

  617. rAUD3LOW EQU rNR33

  618. 

  619. 

  620. ; --

  621. ; -- AUD3HIGH/NR34 ($FF1E)

  622. ; -- Frequency hi (W)

  623. ; --

  624. ; -- see AUD1HIGH for info

  625. ; --

  626. rNR34 EQU $FF1E

  627. rAUD3HIGH EQU rNR34

  628. 

  629. 

  630. ; --

  631. ; -- AUD4LEN/NR41 ($FF20)

  632. ; -- Sound length (R/W)

  633. ; --

  634. ; -- Bit 5-0 - Sound length data (# 0-63)

  635. ; --

  636. rNR41 EQU $FF20

  637. rAUD4LEN EQU rNR41

  638. 

  639. 

  640. ; --

  641. ; -- AUD4ENV/NR42 ($FF21)

  642. ; -- Envelope (R/W)

  643. ; --

  644. ; -- see AUD1ENV for info

  645. ; --

  646. rNR42 EQU $FF21

  647. rAUD4ENV EQU rNR42

  648. 

  649. 

  650. ; --

  651. ; -- AUD4POLY/NR43 ($FF22)

  652. ; -- Polynomial counter (R/W)

  653. ; --

  654. ; -- Bit 7-4 - Selection of the shift clock frequency of the (scf)

  655. ; --           polynomial counter (0000-1101)

  656. ; --           freqEQUdrf*1/2^scf (not sure)

  657. ; -- Bit 3 -   Selection of the polynomial counter's step

  658. ; --           0: 15 steps

  659. ; --           1: 7 steps

  660. ; -- Bit 2-0 - Selection of the dividing ratio of frequencies (drf)

  661. ; --           000: f/4   001: f/8   010: f/16  011: f/24

  662. ; --           100: f/32  101: f/40  110: f/48  111: f/56  (fEQU4.194304 Mhz)

  663. ; --

  664. rNR43 EQU $FF22

  665. rAUD4POLY EQU rNR43

  666. 

  667. 

  668. ; --

  669. ; -- AUD4GO/NR44 ($FF23)

  670. ; -- (has wrong name and value (ff30) in Dr.Pan's doc!)

  671. ; --

  672. ; -- Bit 7 -   Inital

  673. ; -- Bit 6 -   Counter/consecutive selection

  674. ; --

  675. rNR44 EQU $FF23

  676. rAUD4GO EQU rNR44 ; silly name!

  677. 

  678. 

  679. ; --

  680. ; -- PCM12 ($FF76)

  681. ; -- Sound channel 1&2 PCM amplitude (R)

  682. ; --

  683. ; -- Bit 7-4 - Copy of sound channel 2's PCM amplitude

  684. ; -- Bit 3-0 - Copy of sound channel 1's PCM amplitude

  685. ; --

  686. rPCM12 EQU $FF76

  687. 

  688. 

  689. ; --

  690. ; -- PCM34 ($FF77)

  691. ; -- Sound channel 3&4 PCM amplitude (R)

  692. ; --

  693. ; -- Bit 7-4 - Copy of sound channel 4's PCM amplitude

  694. ; -- Bit 3-0 - Copy of sound channel 3's PCM amplitude

  695. ; --

  696. rPCM34 EQU $FF77

  697. 

  698. 

  699. ;***************************************************************************

  700. ;*

  701. ;* Flags common to multiple sound channels

  702. ;*

  703. ;***************************************************************************

  704. 

  705. ; --

  706. ; -- Square wave duty cycle

  707. ; --

  708. ; -- Can be used with AUD1LEN and AUD2LEN

  709. ; -- See AUD1LEN for more info

  710. ; --

  711. AUDLEN_DUTY_12_5    EQU %00000000 ; 12.5%

  712. AUDLEN_DUTY_25      EQU %01000000 ; 25%

  713. AUDLEN_DUTY_50      EQU %10000000 ; 50%

  714. AUDLEN_DUTY_75      EQU %11000000 ; 75%

  715. 

  716. 

  717. ; --

  718. ; -- Audio envelope flags

  719. ; --

  720. ; -- Can be used with AUD1ENV, AUD2ENV, AUD4ENV

  721. ; -- See AUD1ENV for more info

  722. ; --

  723. AUDENV_UP           EQU %00001000

  724. AUDENV_DOWN         EQU %00000000

  725. 

  726. 

  727. ; --

  728. ; -- Audio trigger flags

  729. ; --

  730. ; -- Can be used with AUD1HIGH, AUD2HIGH, AUD3HIGH

  731. ; -- See AUD1HIGH for more info

  732. ; --

  733. 

  734. AUDHIGH_RESTART     EQU %10000000

  735. AUDHIGH_LENGTH_ON   EQU %01000000

  736. AUDHIGH_LENGTH_OFF  EQU %00000000

  737. 

  738. 

  739. ;***************************************************************************

  740. ;*

  741. ;* Cart related

  742. ;*

  743. ;***************************************************************************

  744. 

  745. CART_COMPATIBLE_DMG     EQU $00

  746. CART_COMPATIBLE_DMG_GBC EQU $80

  747. CART_COMPATIBLE_GBC     EQU $C0

  748. 

  749. CART_ROM                     EQU $00

  750. CART_ROM_MBC1                EQU $01

  751. CART_ROM_MBC1_RAM            EQU $02

  752. CART_ROM_MBC1_RAM_BAT        EQU $03

  753. CART_ROM_MBC2                EQU $05

  754. CART_ROM_MBC2_BAT            EQU $06

  755. CART_ROM_RAM                 EQU $08

  756. CART_ROM_RAM_BAT             EQU $09

  757. CART_ROM_MBC3_BAT_RTC        EQU $0F

  758. CART_ROM_MBC3_RAM_BAT_RTC    EQU $10

  759. CART_ROM_MBC3                EQU $11

  760. CART_ROM_MBC3_RAM            EQU $12

  761. CART_ROM_MBC3_RAM_BAT        EQU $13

  762. CART_ROM_MBC5                EQU $19

  763. CART_ROM_MBC5_BAT            EQU $1A

  764. CART_ROM_MBC5_RAM_BAT        EQU $1B

  765. CART_ROM_MBC5_RUMBLE         EQU $1C

  766. CART_ROM_MBC5_RAM_RUMBLE     EQU $1D

  767. CART_ROM_MBC5_RAM_BAT_RUMBLE EQU $1E

  768. CART_ROM_MBC7_RAM_BAT_GYRO   EQU $22

  769. CART_ROM_POCKET_CAMERA       EQU $FC

  770. 

  771. CART_ROM_256K EQU 0 ; 2 banks

  772. CART_ROM_512K EQU 1 ; 4 banks

  773. CART_ROM_1M   EQU 2 ; 8 banks

  774. CART_ROM_2M   EQU 3 ; 16 banks

  775. CART_ROM_4M   EQU 4 ; 32 banks

  776. CART_ROM_8M   EQU 5 ; 64 banks

  777. CART_ROM_16M  EQU 6 ; 128 banks

  778. CART_ROM_32M  EQU 7 ; 256 banks

  779. CART_ROM_64M  EQU 8 ; 512 banks

  780. 

  781. CART_RAM_NONE EQU 0

  782. CART_RAM_16K  EQU 1 ; 1 incomplete bank

  783. CART_RAM_64K  EQU 2 ; 1 bank

  784. CART_RAM_256K EQU 3 ; 4 banks

  785. CART_RAM_1M   EQU 4 ; 16 banks

  786. 

  787. CART_RAM_ENABLE  EQU $0A

  788. CART_RAM_DISABLE EQU $00

  789. 

  790. ;***************************************************************************

  791. ;*

  792. ;* Keypad related

  793. ;*

  794. ;***************************************************************************

  795. 

  796. PADF_DOWN   EQU $80

  797. PADF_UP     EQU $40

  798. PADF_LEFT   EQU $20

  799. PADF_RIGHT  EQU $10

  800. PADF_START  EQU $08

  801. PADF_SELECT EQU $04

  802. PADF_B      EQU $02

  803. PADF_A      EQU $01

  804. 

  805. PADB_DOWN   EQU $7

  806. PADB_UP     EQU $6

  807. PADB_LEFT   EQU $5

  808. PADB_RIGHT  EQU $4

  809. PADB_START  EQU $3

  810. PADB_SELECT EQU $2

  811. PADB_B      EQU $1

  812. PADB_A      EQU $0

  813. 

  814. ;***************************************************************************

  815. ;*

  816. ;* Screen related

  817. ;*

  818. ;***************************************************************************

  819. 

  820. SCRN_X    EQU 160 ; Width of screen in pixels

  821. SCRN_Y    EQU 144 ; Height of screen in pixels

  822. SCRN_X_B  EQU 20  ; Width of screen in bytes

  823. SCRN_Y_B  EQU 18  ; Height of screen in bytes

  824. 

  825. SCRN_VX   EQU 256 ; Virtual width of screen in pixels

  826. SCRN_VY   EQU 256 ; Virtual height of screen in pixels

  827. SCRN_VX_B EQU 32  ; Virtual width of screen in bytes

  828. SCRN_VY_B EQU 32  ; Virtual height of screen in bytes

  829. 

  830. ;*

  831. ;* Nintendo scrolling logo

  832. ;* (Code won't work on a real GameBoy)

  833. ;* (if next lines are altered.)

  834. NINTENDO_LOGO : MACRO

  835.     DB  $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D

  836.     DB  $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99

  837.     DB  $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E

  838. ENDM

  839. 

  840.     ENDC ;HARDWARE_INC