lr35902ish racket
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README.md 2.8KB

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  1. # zybino: LR35902ish racket language
  2. very early days for now.
  3. in the racket repl (comments for reader comprehension, remove before running):
  4. ```
  5. (run-vm #x150 #x150 #x19 ; start-address, end-memory-view-addr, number-bytes-view
  6. '(#x3E #x69 ; LD A, $69
  7. #x26 #x01 ; LD H, $01
  8. #x2E #x67 ; LD L, $67
  9. #x77 ; LD (HL), A
  10. #x2E #x5B ; LD L, $5B
  11. #x36 #xE6 ; LD (HL), $E6 ($E6 is the opcode for XOR $xx)
  12. #x10 ; STOP (this instruction @ address $015B)
  13. #xF0 ; (non-instruction, will be arg for previous byte)
  14. #x2E #x68 ; LD L, $68
  15. #x77 ; LD (HL), A
  16. #xC2 #x64 #x01 ; JP NZ, $0164
  17. #x10 ; STOP
  18. #x7D ; LD A, L (address $0164)
  19. #x10 ; STOP
  20. ))
  21. ```
  22. will evaluate to:
  23. ```
  24. PC: $0166, SP: $0000, Flags: %00000000
  25. BC: $0000, DE: $0000
  26. HL: $0168, AF: $6800
  27. (HL): $60
  28. $0150 > $3e $69 $26 $01 $2e $67 $77 $2e $5b $36 $e6 $e6 $f0 $2e $68 $77 $c3 $64 $01 $10 $7d $10 $00 $69 $60 < $0168
  29. ```
  30. here we can see the program loaded starting from address `$0150`, including the `XOR` instruction loaded to `$015B` during execution, and the `$69` we loaded to memory, along with the result of `XOR $F0` we loaded to memory, at `$0167` and `$0168` respectively. we can also see that the `A` register is `$68`, the same as the `L` register, as the conditional `JP NZ` instruction executed properly and we skipped the `STOP` at address `$0163`.
  31. ## example 2 - loops
  32. running:
  33. ```
  34. (run-vm #x0000 #x0160 8
  35. '(#x26 #x01 ; LD H, $01
  36. #x2E #x61 ; LD L, $60
  37. #x3E #x05 ; LD A, $05
  38. #x77 ; LD (HL), A
  39. #x2C ; INC L
  40. #x3D ; DEC A
  41. #xFE #x00 ; CP $00
  42. #xC2 #x06 #x00 ; JP NZ, $0008
  43. #x10 ; STOP
  44. )))
  45. ```
  46. evaluates to:
  47. ```
  48. PC: $000f, SP: $0000, Flags: %10000000
  49. BC: $0000, DE: $0000
  50. HL: $0166, AF: $0080
  51. (HL): $00
  52. $0160 > $00 $05 $04 $03 $02 $01 $00 $00 < $0167
  53. ```
  54. where we can see the zero flag set (bit 7), thus triggering the conditional loop, and the result of our loop saved to addresses `$0161` to `$0166`
  55. ## notes
  56. currently supported instructions are:
  57. * `JP #addr`
  58. * `JP [cc], #addr`
  59. * `LD [reg], #imm`
  60. * `LD [reg], [reg]`
  61. * `XOR #imm`
  62. * `AND #imm`
  63. * `OR #imm`
  64. * `ADD #imm`
  65. * `ADC #imm`
  66. * `SUB #imm`
  67. * `SBC #imm`
  68. * `CP #imm`
  69. * `XOR [reg]`
  70. * `AND [reg]`
  71. * `OR [reg]`
  72. * `ADD [reg]`
  73. * `ADC [reg]`
  74. * `SUB [reg]`
  75. * `SBC [reg]`
  76. * `CP [reg]`
  77. * `INC [reg]`
  78. * `DEC [reg]`
  79. * `STOP`
  80. * `NOP`
  81. all other instructions treated as `NOP`
  82. on a gameboy, the instruction `LD (HL), (HL)` is treated as a `HALT`, however i am not making a gameboy perfect vm as of now, so opcode `$76` is currently treated as `LD (HL), (HL)`