62 lines
4.6 KiB
Markdown
Executable File
62 lines
4.6 KiB
Markdown
Executable File
# SYSENTER — Fast System Call
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## Description
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Executes a fast call to a level 0 system procedure or routine. SYSENTER is a companion instruction to SYSEXIT. The instruction is optimized to
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provide the maximum performance for system calls from user code running at privilege level 3 to operating system or executive procedures
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running at privilege level 0.
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## Instruction
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| Opcode | Assembly | Op/En | Modern Mode | Legacy Mode | Description |
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|--------|----------|-------|-------------|-------------|--------------------------------------------------------------------------------------|
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| 0F 34 | SYSENTER | NP | Valid | Valid | Fast call to privilege level 0 system procedures. |
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## Information
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When executed in IA-32e mode, the SYSENTER instruction transitions the logical processor to 64-bit mode; otherwise, the logical processor
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remains in protected mode.
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Prior to executing the SYSENTER instruction, software must specify the privilege level 0 code segment and code entry point, and the privilege
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level 0 stack segment and stack pointer by writing values to the following MSRs: - IA32_SYSENTER_CS (MSR address 174H) — The lower 16 bits of
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this MSR are the segment selector for the privilege level 0 code segment. This value is also used to determine the segment selector of the
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privilege level 0 stack segment (see the Operation section). This value cannot indicate a null selector.
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- IA32_SYSENTER_EIP (MSR address 176H) — The value of this MSR is loaded into RIP (thus, this value references the first instruction of the
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selected operating procedure or routine). In protected mode, only bits 31:0 are loaded.
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- IA32_SYSENTER_ESP (MSR address 175H) — The value of this MSR is loaded into RSP (thus, this value contains the stack pointer for the
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privilege level 0 stack). This value cannot represent a non-canonical address. In protected mode, only bits 31:0 are loaded.
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These MSRs can be read from and written to using RDMSR/WRMSR. The WRMSR instruction ensures that the IA32_SYSENTER_EIP and IA32_SYSENTER_ESP
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MSRs always contain canonical addresses.
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While SYSENTER loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS MSR, the CS and SS descriptor caches are not loaded
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from the descriptors (in GDT or LDT) referenced by those selectors. Instead, the descriptor caches are loaded with fixed values. See the
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Operation section for details. It is the responsibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those
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selector values correspond to the fixed values loaded into the descriptor caches; the SYSENTER instruction does not ensure this correspondence.
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The SYSENTER instruction can be invoked from all operating modes except real-address mode.
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The SYSENTER and SYSEXIT instructions are companion instructions, but they do not constitute a call/return pair. When executing a SYSENTER
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instruction, the processor does not save state information for the user code (e.g., the instruction pointer), and neither the SYSENTER nor the
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SYSEXIT instruction supports passing parameters on the stack.
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To use the SYSENTER and SYSEXIT instructions as companion instructions for transitions between privilege level 3 code and privilege level 0
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operating system procedures, the following conventions must be followed:
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- The segment descriptors for the privilege level 0 code and stack segments and for the privilege level 3 code and stack segments must be
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contiguous in a descriptor table. This convention allows the processor to compute the segment selectors from the value entered in the
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SYSENTER_CS_MSR MSR.
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- The fast system call "stub" routines executed by user code (typically in shared libraries or DLLs) must save the required return IP and
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processor state information if a return to the calling procedure is required. Likewise, the operating system or executive procedures called
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with SYSENTER instructions must have access to and use this saved return and state information when returning to the user code.
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The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor. The availability of these
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instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature flag returned to the EDX register by the CPUID
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instruction. An operating system that qualifies the SEP flag must also qualify the processor family and model to ensure that the
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SYSENTER/SYSEXIT instructions are actually present.
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When the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP flag as set, but does not
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support the SYSENTER/SYSEXIT instructions.
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