Virgil Dupras
8009270e79
Optimize parsing words
2020-05-02 20:32:20 -04:00
Virgil Dupras
931c812394
Remove cmp
...
Not worth the complexity and space.
2020-05-02 19:57:56 -04:00
Virgil Dupras
0b3a328e65
Add a layer of indirection for KEY
2020-05-02 11:17:28 -04:00
Virgil Dupras
446a58006d
Remove one of the 2 indirection layers for EMIT
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2 was overkill
2020-05-02 10:26:34 -04:00
Virgil Dupras
443ed754e9
trs80: add missing blk
2020-05-02 08:27:24 -04:00
Virgil Dupras
3a27479f2b
fix stupid typo
...
I don't believe this, one hour of my life I'll never get back.
2020-05-02 08:06:37 -04:00
Virgil Dupras
b8d8007a3f
trs80: add *CL< and *CL>
2020-05-02 06:20:03 -04:00
Virgil Dupras
2a578b3352
editor: implement F
2020-05-01 21:52:38 -04:00
Virgil Dupras
86539d2a03
Fix tests
2020-05-01 20:09:51 -04:00
Virgil Dupras
ecca70c7f3
Add layer of indirection to EMIT
...
This would allow things like temporary giving control to the *CL
line on the TRS-80. For example... A very far fetched example. Not
at all the only *raison d'etre* of the layer...
2020-05-01 20:05:15 -04:00
Virgil Dupras
5bf3baff05
editor: add edit buffer
...
Also, add word "C!+" and fix PSP leak in FILL.
2020-05-01 13:17:40 -04:00
Virgil Dupras
792c781614
editor: add cursor pos tracking and display
2020-04-30 20:42:07 -04:00
Virgil Dupras
07f807edee
recipes/trs80: making progress on floppy drivers
2020-04-30 16:10:35 -04:00
Virgil Dupras
65f359bda4
recipes/trs80: can write compiled version to floppy
2020-04-30 11:13:25 -04:00
Virgil Dupras
f38de1c151
Introduce the notion of Extra words
2020-04-29 21:52:18 -04:00
Virgil Dupras
0044011f06
Move AT28 and TRS80 drivers to higher blocknos
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I'm reserving the 100-200 range for non-bootstrapping needs.
2020-04-29 21:04:10 -04:00
Virgil Dupras
0cf26547ff
Add words FLUSH and COPY
2020-04-29 20:21:18 -04:00
Virgil Dupras
581f04a4bc
Keep stage1 bootstrap bin instead of stage 0
...
XPACKed source needing to be kept in bootstrap bin didn't make
much sense. With the removal of stripfc, it makes more sense to keep
the compiled form of stage 1 in repository as a bootstrap binary.
Also, rename it to forth.bin.
2020-04-29 19:38:43 -04:00
Virgil Dupras
b046aba7f9
recipes/trs80: running!
...
no floppy yet.
2020-04-29 12:26:44 -04:00
Virgil Dupras
1b2c4b519e
icore: add BIN+
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This allows us to write LATEST at proper offset in emul/stage1.fs in
cases where we set a nonzero BIN(.
2020-04-29 11:42:09 -04:00
Virgil Dupras
fc67b88720
Make BIN( offsetted binaries closer to working at all
...
I have a working offset-by-0x100 stage0 now.
2020-04-28 21:12:52 -04:00
Virgil Dupras
0b8c8c9ca0
recipes/trs80: still wip...
2020-04-28 10:12:16 -04:00
Virgil Dupras
61b2e02351
xcomp: remove XOFF and use ORG and BIN( instead
2020-04-28 09:37:00 -04:00
Virgil Dupras
838548843e
boot: apply BIN( to stray stable ABI references
...
With cross compiling and IMMEDIATE words, things get icky with stable
ABI references. For the same reason that EXIT, (br) and (br?) need to
stay at stable offsets, these word references will not have BIN(
properly applied at Inner core xcomp.
The solution for now is to adjust during EXECUTE, which is ugly and
inefficient, but I don't see a better solution right now.
2020-04-28 08:52:47 -04:00
Virgil Dupras
4501313410
Add [IF] .. [THEN]
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Will be useful as kinds of "#ifdef"s during xcomp.
2020-04-28 08:28:59 -04:00
Virgil Dupras
f97df4614e
recipes/trs80: wip
2020-04-28 07:51:41 -04:00
Virgil Dupras
b8ea515612
Add word WIPE
2020-04-27 21:28:34 -04:00
Virgil Dupras
2b2ccad96c
Add word FILL
2020-04-27 21:22:06 -04:00
Virgil Dupras
f605e2d85c
Give CASE's default branch access to its input value
...
ref #97
2020-04-27 20:44:21 -04:00
Virgil Dupras
3b66aefcd1
block editor: fix broken B and N
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fixes #97
2020-04-27 18:11:54 -04:00
Virgil Dupras
295b4b6e0a
z80a: add BIN( parameter
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Will be useful for assembling binaries for the TRS-80 which can't start
at addr 0.
2020-04-27 15:11:38 -04:00
Virgil Dupras
ee79df225e
typo
2020-04-27 09:44:37 -04:00
Virgil Dupras
efed0e249e
recipes/rc2014/selfhost: add verification instructions
2020-04-27 09:24:40 -04:00
Virgil Dupras
6c51ea1ebb
recipes/rc2014/selfhost: complete instructions
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I have yet to test the whole process on real hardware. Soon.
2020-04-26 20:20:36 -04:00
Virgil Dupras
f690cb2e5b
recipes/rc2014/sdcard: use driver from blkfs
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This completes the migration of all Collapse OS code into blkfs!
2020-04-26 19:50:38 -04:00
Virgil Dupras
865f4f9256
Move AT28 driver to blkfs
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And adjust rc2014/eeprom recipe
2020-04-26 15:18:28 -04:00
Virgil Dupras
7c692c1111
recipes/rc2014: include readln directly in stage 1
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XPACK is more efficient than stripfc was, we can pack more stuff in 8K.
We now have enough space to fit readln.
2020-04-26 14:52:55 -04:00
Virgil Dupras
dee7eea497
Move link.fs to blkfs
2020-04-26 14:37:54 -04:00
Virgil Dupras
4d8574c1fe
recipe/rc2014: use core libs from blkfs
2020-04-26 13:57:44 -04:00
Virgil Dupras
a2f164ecc3
emul: bootstrap to stage2 from within Collapse OS!
...
Big bootstrapping change which greatly reduces the role of the modern
operating system in the bootstrapping process.
2020-04-26 10:24:09 -04:00
Virgil Dupras
0e3cf7fa02
Add word ,"
2020-04-26 09:01:49 -04:00
Virgil Dupras
4b7247a971
emul: use LATEST instead of binary size as start addr in stage
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More reliable.
2020-04-26 08:37:12 -04:00
Virgil Dupras
898684a795
emul: merge pre.fs and emul.fs into stage1.fs
2020-04-25 22:45:53 -04:00
Virgil Dupras
bc3aabc84e
Update z80c.bin's LATEST during xcomp instead of using slatest
2020-04-25 22:02:44 -04:00
Virgil Dupras
6f896caf7a
Copy core words to blkfs
2020-04-25 21:54:07 -04:00
Virgil Dupras
6767012ebd
recipe/rc2014/selfhost: new recipe
2020-04-25 19:24:55 -04:00
Virgil Dupras
13771d8c92
xcomp: add XPACK
2020-04-25 16:02:47 -04:00
Virgil Dupras
389b23fe1a
Change C<? mechanic
...
It's now a simple flag updated by the C< implementation. No more
routine pointer.
The goal is to avoid tons of "ok" during a LOAD operation.
2020-04-25 09:10:25 -04:00
Virgil Dupras
4160c8ebbf
recipes/rc2014: busting the 8K limit again!
2020-04-25 08:15:17 -04:00
Virgil Dupras
5219887ad7
sdc: implement _crc16 in z80
2020-04-24 20:46:01 -04:00